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[AArch64] Improve FP16 instruction selection for vector round and vector convert from half instructions
AcceptedPublic

Authored by az on Mar 1 2019, 4:27 PM.

Details

Reviewers
SjoerdMeijer
Summary

We currently generate inefficient code for vector rounding and vector convert from half due to minor issues in instruction selection lowering. Fix those issues related to checking for the fullfp16 support (for convert instruction) and initialization (for round instruction).

Diff Detail

Event Timeline

az created this revision.Mar 1 2019, 4:27 PM
This revision is now accepted and ready to land.Mar 5 2019, 1:10 AM