[AMDGPU] fix commuted case of sub combine

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

8621 ↗

(On Diff #187692)

This swap is hard to follow. It's not immediately clear to me why this would be commuted in != subcarry case. What happens in the sub (subcarry, subcarry) case? I think it would be clearer to just explicitly handle the two cases

8625 ↗

(On Diff #187692)

This needs a comment with the commuted case

8626–8627 ↗

(On Diff #187692)

This can use C->isNullValue() instead of getZExtValue

test/CodeGen/AMDGPU/combine-cond-add-sub.ll

151 ↗

(On Diff #187692)

Maybe add a test where both operands to a sub are subcarry

[rampitec]

lib/Target/AMDGPU/SIISelLowering.cpp

8621 ↗

(On Diff #187692)

It really does not matter what is the RHS, it can be anything including subcarry.

test/CodeGen/AMDGPU/combine-cond-add-sub.ll

151 ↗

(On Diff #187692)

That is really no different from any other instruction but complicates the test a lot since we cannot get subcarry right from the IR.

[arsenm]

LGTM

[rampitec]

Actually I think it is still wrong. In the commuted case carry must be added, not subtracted:

x - (y - 0 - cc) => x - y + cc

I will just disable it for commuted case.

[rampitec]

Disabled commuted case completely.

[arsenm]

test/CodeGen/AMDGPU/combine-cond-add-sub.ll

131–133 ↗

(On Diff #187707)

This needs operand checks

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::performSubCombine(SDNode *N,
 
   if (VT != MVT::i32)
     return SDValue();
 
   SDLoc SL(N);
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
 
-  unsigned Opc = LHS.getOpcode();
-  if (Opc != ISD::SUBCARRY)
-    std::swap(RHS, LHS);
-
   if (LHS.getOpcode() == ISD::SUBCARRY) {
     // sub (subcarry x, 0, cc), y => subcarry x, y, cc
     auto C = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
-    if (!C || C->getZExtValue() != 0)
+    if (!C || !C->isNullValue())
       return SDValue();
     SDValue Args[] = { LHS.getOperand(0), RHS, LHS.getOperand(2) };
     return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);
   }
   return SDValue();
 }
 
 SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,

llvm/trunk/test/CodeGen/AMDGPU/combine-cond-add-sub.ll

bb:
   %cmp = icmp ugt i32 %x, %y
   %ext = sext i1 %cmp to i32
   %adde = add i32 %v, %ext
   %sub = sub i32 %adde, %a
   store i32 %sub, i32 addrspace(1)* %gep, align 4
   ret void
 }
 
+; GCN-LABEL: {{^}}sub_sube_commuted:
+; GCN-DAG: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: buffer_load_dword [[V:v[0-9]+]],
+; GCN:     v_subbrev_u32_e{{32|64}} [[SUBB:v[0-9]+]], {{[^,]+}}, 0, [[V]], [[CC]]
+; GCN:     v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, s{{[0-9]+}}, [[SUBB]]
+; GCN:     v_add_i32_e32 {{.*}}, 0x64, [[SUB]]
+
+; GFX9-LABEL: {{^}}sub_sube_commuted:
+; GFX9-DAG: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GFX9-DAG: global_load_dword [[V:v[0-9]+]],
+; GFX9:     v_subbrev_co_u32_e{{32|64}} [[SUBB:v[0-9]+]], {{[^,]+}}, 0, [[V]], [[CC]]
+; GFX9:     v_sub_u32_e32 [[SUB:v[0-9]+]], s{{[0-9]+}}, [[SUBB]]
+; GFX9:     v_add_u32_e32 {{.*}}, 0x64, [[SUB]]
+define amdgpu_kernel void @sub_sube_commuted(i32 addrspace(1)* nocapture %arg, i32 %a) {
+bb:
+  %x = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %y = tail call i32 @llvm.amdgcn.workitem.id.y()
+  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
+  %v = load i32, i32 addrspace(1)* %gep, align 4
+  %cmp = icmp ugt i32 %x, %y
+  %ext = sext i1 %cmp to i32
+  %adde = add i32 %v, %ext
+  %sub = sub i32 %adde, %a
+  %sub2 = sub i32 100, %sub
+  store i32 %sub2, i32 addrspace(1)* %gep, align 4
+  ret void
+}
+
 ; GCN-LABEL: {{^}}sube_sub:
 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
 ; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
 ; GCN-NOT: v_cndmask
 ; GCN-NOT: v_sub
 
 ; GFX9-LABEL: {{^}}sube_sub:
 ; GFX9: v_subb_co_u32_e{{32|64}} v{{[0-9]+}}, vcc