Hexagon: Add ImmArg to intrinsics

[arsenm]

Summary

I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.

[kparzysz]

I don't really understand the summary, could you elaborate on how the asserting implies the conclusion (the part that follows "This means that..."). Also, what does that part mean on its own? "Intrinsics are missing that don't use GCCBuiltin...", meaning that you'd expect some intrinsics that don't use GCCBuiltin, but they're not defined?

[arsenm]

In D58356#1401300, @kparzysz wrote:

I don't really understand the summary, could you elaborate on how the asserting implies the conclusion (the part that follows "This means that..."). Also, what does that part mean on its own? "Intrinsics are missing that don't use GCCBuiltin...", meaning that you'd expect some intrinsics that don't use GCCBuiltin, but they're not defined?

The assert can't catch all possible cases which may exist, so this may not be complete without someone with knowledge of these intrinsics auditing them.

GCCBuiltin is an annotation on the LLVM IR intrinsic which doesn't really do anything on its own. GCCBuiltin also doesn't support intrinsics that use name mangling (you would need to be able to specify one for each mangling you want to support in the frontend). There has to be a corresponding builtin definition explicitly defined in clang, which also needs to correctly mark the required constant operands. The test coverage for which operands need to be constants is spotty or nonexistent for these, so those are possibly missing in the builtin definition.

[kparzysz]

In D58356#1401321, @arsenm wrote:

There has to be a corresponding builtin definition explicitly defined in clang, which also needs to correctly mark the required constant operands. The test coverage for which operands need to be constants is spotty or nonexistent for these, so those are possibly missing in the builtin definition.

So you added the assertion to clang and ran clang-check? This patch is missing information for S2_insert (that's one case that found by just looking at it), but the builtin for S2_insert is both marked properly in BuiltinsHexagon.def, and is run through clang codegen tests.

About this thing in particular:

The test coverage for which operands need to be constants is spotty or nonexistent for these, so those are possibly missing in the builtin definition.

Yes, we only test a few cases to see if the SemaCheck machinery works, I'm not sure if that's what you're referring to. There are a lot more builtins tested for codegen, which should still go through the same checks (this includes the S2_insert builtin, which is not annotated in this patch).

Was the S2_insert omitted because you missed it when you were editing the .td file, or because your testing didn't find it? From your description so far, all I really know is that you added an assertion somewhere, the rest is really vague.

[kparzysz]

I'm not expecting this patch to be complete. Most of the intrinsic definitions are actually auto-generated, so we'll need to update the generating scripts to include these new annotations. What concerns me is that you claim that some things are missing, which could indicate that there are some issues with the generators. I'm trying to understand exactly what the missing pieces are, the contents of this patch are actually of secondary importance.

[arsenm]

In D58356#1401354, @kparzysz wrote:

In D58356#1401321, @arsenm wrote:

There has to be a corresponding builtin definition explicitly defined in clang, which also needs to correctly mark the required constant operands. The test coverage for which operands need to be constants is spotty or nonexistent for these, so those are possibly missing in the builtin definition.

So you added the assertion to clang and ran clang-check? This patch is missing information for S2_insert (that's one case that found by just looking at it), but the builtin for S2_insert is both marked properly in BuiltinsHexagon.def, and is run through clang codegen tests.

About this thing in particular:

The test coverage for which operands need to be constants is spotty or nonexistent for these, so those are possibly missing in the builtin definition.

Yes, we only test a few cases to see if the SemaCheck machinery works, I'm not sure if that's what you're referring to. There are a lot more builtins tested for codegen, which should still go through the same checks (this includes the S2_insert builtin, which is not annotated in this patch).

Yes, there isn't test coverage to make sure each builtin is properly marked for constant arguments.

Was the S2_insert omitted because you missed it when you were editing the .td file, or because your testing didn't find it? From your description so far, all I really know is that you added an assertion somewhere, the rest is really vague.

I didn't find it, I'll try to figure out why.

[arsenm]

In D58356#1401366, @kparzysz wrote:

I'm not expecting this patch to be complete. Most of the intrinsic definitions are actually auto-generated, so we'll need to update the generating scripts to include these new annotations. What concerns me is that you claim that some things are missing, which could indicate that there are some issues with the generators. I'm trying to understand exactly what the missing pieces are, the contents of this patch are actually of secondary importance.

I'm not claiming I know it's incomplete, it's just there are reasons the method for finding them can't catch 100% of cases. In hexagon's case in particular GCCBuiltin seems to be consistently used, so the coverage is probably better

[arsenm]

In D58356#1401381, @arsenm wrote:

Was the S2_insert omitted because you missed it when you were editing the .td file, or because your testing didn't find it? From your description so far, all I really know is that you added an assertion somewhere, the rest is really vague.

I didn't find it, I'll try to figure out why.

S2_insert is covered, it's just handled inside Hexagon_i32_i32i32i32i32_Intrinsic

[kparzysz]

I see. Thanks for looking into it.

In any case, most of this file will be regenerated with the necessary annotations anyways, so if something's missing now it will be included later on.

[arsenm]

r356092

include/llvm/IR/IntrinsicsHexagon.td

: Hexagon_Intrinsic<GCCIntSuffix,
                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
                            llvm_i32_ty],
                           [IntrWriteMem]>;
 
 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
                            llvm_i32_ty, llvm_i32_ty],
-                          [IntrArgMemOnly]>;
+                          [IntrArgMemOnly, ImmArg<3>]>;
 
 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
                            llvm_i32_ty, llvm_i32_ty],
-                          [IntrWriteMem]>;
+                          [IntrWriteMem, ImmArg<3>]>;
 
 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
                            llvm_i32_ty, llvm_i32_ty],
-                          [IntrWriteMem]>;
+                          [IntrWriteMem, ImmArg<3>]>;
 
 //
 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
 //
 def int_hexagon_circ_ldd :
 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
 //
 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)

 
 // tag : V6_vrmpybusv
 class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vaslw_acc
-class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
+                                               list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vaslw_acc
-class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
+                                               list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vmux
 class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vmux
 class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
        [IntrNoMem]>;
 
 // tag : S2_tableidxd_goodsyntax
 class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       [IntrNoMem, ImmArg<2>, ImmArg<3>]>;
 
 // tag : V6_vandnqrt_acc
 class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vandnqrt_acc
 class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vrmpybusi
-class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vrmpybusi
-class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,
+                                            list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vsubb_dv
-class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : M2_mpysu_up
-class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,
+                                   list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : M2_mpyud_acc_ll_s0
-class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : S2_lsr_i_r_nac
-class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,
+                                             list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : M2_cmpysc_s0
-class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_lo
-class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v32i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_lo
-class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v64i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : S2_shuffoh
 class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
        [IntrNoMem]>;
 
 // tag : F2_sfmax

 
 // tag : V6_vdmpyhb
 class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : A4_vcmphgti
-class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag :
 class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : S6_rol_i_p_or
-class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,
+                                      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vgtuh_and
 class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vgtuh_and
 class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
        [IntrNoMem]>;
 
 // tag : A2_abssat
-class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,
+                                list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : A2_vcmpwgtu
-class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,
+                                  list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vtmpybus_acc
 class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : F2_conv_df2uw_chop

 
 // tag : V6_pred_or
 class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
        [IntrNoMem]>;
 
 // tag : S2_asr_i_p_rnd_goodsyntax
-class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : F2_conv_w2df
-class Hexagon_double_i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_double_ty], [llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vunpackuh
 class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vunpackuh

 
 // tag : V6_extractw
 class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vlutvwhi
-class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vlutvwhi
-class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vgtuh
 class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vgtuh

 
 // tag : F2_conv_ud2df
 class Hexagon_double_i64_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_double_ty], [llvm_i64_ty],
        [IntrNoMem]>;
 
 // tag : S2_vzxthw
-class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vtmpyhb
 class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vshufoeh

 
 // tag :
 class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : F2_conv_uw2sf
-class Hexagon_float_i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_float_ty], [llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vswap
 class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vswap

 
 // tag : V6_vaddcarrysat
 class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
        [IntrNoMem]>;
 
 // tag : V6_vlutvvb_oracc
-class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
+                                                     list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vlutvvb_oracc
-class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vrmpybub_rtt
 class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
        [IntrNoMem]>;
 
 // tag : V6_vrmpybub_rtt
 class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
        [IntrNoMem]>;
 
 // tag : A4_addp_c
 class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vrsadubi_acc
-class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,
+                                                  list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vrsadubi_acc
-class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : F2_conv_df2sf
 class Hexagon_float_double_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_float_ty], [llvm_double_ty],
        [IntrNoMem]>;
 
 // tag : V6_vandvqv

 
 // tag : V6_vmpyowh_sacc
 class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
        [IntrNoMem]>;
 
 // tag : S2_insertp
-class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,
+                                         list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : F2_sfinvsqrta
 class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_float_ty,llvm_i32_ty], [llvm_float_ty],
        [IntrNoMem, Throws]>;
 
 // tag : V6_vtran2x2_map
 class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vtran2x2_map
 class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
        [IntrNoMem]>;
 
 // tag : V6_vlutvwh_oracc
-class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : V6_vlutvwh_oracc
-class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
+class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
+      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
-       [IntrNoMem]>;
+       !listconcat([IntrNoMem], intr_properties)>;
 
 // tag : F2_dfcmpge
 class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],
        [IntrNoMem, Throws]>;
 
 // tag : F2_conv_df2d_chop
 class Hexagon_i64_double_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_double_ty],
        [IntrNoMem]>;
 
 // tag : F2_conv_sf2w
 class Hexagon_i32_float_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_float_ty],
        [IntrNoMem]>;
 
 // tag : F2_sfclass
 class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],
-       [IntrNoMem, Throws]>;
+       [IntrNoMem, Throws, ImmArg<1>]>;
 
 // tag : F2_conv_sf2ud_chop
 class Hexagon_i64_float_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i64_ty], [llvm_float_ty],
        [IntrNoMem]>;
 
 // tag : V6_pred_scalar2v2

 
 // tag : F2_sffma_sc
 class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],
        [IntrNoMem, Throws]>;
 
 // tag : F2_dfclass
-class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix>
+class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,
+                                      list<IntrinsicProperty> intr_properties = []>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],
-       [IntrNoMem, Throws]>;
+       !listconcat([IntrNoMem, Throws], intr_properties)>;
 
 // tag : V6_vd0
 class Hexagon_v16i32__Intrinsic<string GCCIntSuffix>
   : Hexagon_Intrinsic<GCCIntSuffix,
        [llvm_v16i32_ty], [],
        [IntrNoMem]>;
 
 // tag : V6_vd0

 
 def int_hexagon_F2_sfmax :
 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">;
 
 def int_hexagon_A2_vabswsat :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;
 
 def int_hexagon_S2_asr_i_r :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [ImmArg<1>]>;
 
 def int_hexagon_S2_asr_i_p :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [ImmArg<1>]>;
 
 def int_hexagon_A4_combineri :
-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri">;
+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
 
 def int_hexagon_M4_vpmpyh_acc :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
 
 def int_hexagon_M2_vcmpy_s0_sat_i :

 
 def int_hexagon_A2_vaddws :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;
 
 def int_hexagon_A2_maxup :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;
 
 def int_hexagon_A4_vcmphgti :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [ImmArg<1>]>;
 
 def int_hexagon_S2_interleave :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;
 
 def int_hexagon_M2_vrcmpyi_s0 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
 
 def int_hexagon_A2_abssat :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;
 
 def int_hexagon_A2_vcmpwgtu :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
 
 def int_hexagon_C2_cmpgtu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;
 
 def int_hexagon_C2_cmpgtp :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;
 
 def int_hexagon_A4_cmphgtui :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [ImmArg<1>]>;
 
 def int_hexagon_C2_cmpgti :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpyi :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;
 
 def int_hexagon_F2_conv_df2uw_chop :
 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
 
 def int_hexagon_A4_cmpheq :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;
 
 def int_hexagon_M2_mpy_lh_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
 
 def int_hexagon_M2_mpy_lh_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
 
 def int_hexagon_S2_lsr_i_r_xacc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [ImmArg<2>]>;
 
 def int_hexagon_S2_vrcnegh :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;
 
 def int_hexagon_S2_extractup :
-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup">;
+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [ImmArg<1>, ImmArg<2>]>;
 
 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [ImmArg<1>]>;
 
 def int_hexagon_S4_ntstbit_r :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;
 
 def int_hexagon_F2_conv_w2sf :
 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;
 
 def int_hexagon_C2_not :

 
 def int_hexagon_A4_cmpbgt :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;
 
 def int_hexagon_S2_asr_r_r_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
 
 def int_hexagon_A4_rcmpneqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_r_nac :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [ImmArg<2>]>;
 
 def int_hexagon_M2_subacc :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;
 
 def int_hexagon_A2_orp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;
 
 def int_hexagon_M2_mpyu_up :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;
 
 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
 
 def int_hexagon_S2_asr_i_vh :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [ImmArg<1>]>;
 
 def int_hexagon_S2_asr_i_vw :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [ImmArg<1>]>;
 
 def int_hexagon_A4_cmpbgtu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;
 
 def int_hexagon_A4_vcmpbeq_any :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
 
 def int_hexagon_A4_cmpbgti :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpyd_lh_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
 
 def int_hexagon_S2_asl_r_p_nac :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
 
 def int_hexagon_S2_lsr_i_r_nac :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [ImmArg<2>]>;
 
 def int_hexagon_A2_addsp :
 Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;
 
 def int_hexagon_S4_vxsubaddw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;
 
 def int_hexagon_A4_vcmpheqi :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [ImmArg<1>]>;
 
 def int_hexagon_S4_vxsubaddh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;
 
 def int_hexagon_M4_pmpyw :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;
 
 def int_hexagon_S2_vsathb :

 
 def int_hexagon_S2_lsl_r_p_acc :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
 
 def int_hexagon_A2_pxorf :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">;
 
 def int_hexagon_C2_cmpgei :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [ImmArg<1>]>;
 
 def int_hexagon_A2_vsubub :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;
 
 def int_hexagon_S2_asl_i_p :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_r :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [ImmArg<1>]>;
 
 def int_hexagon_A4_vrminuw :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;
 
 def int_hexagon_F2_sffma :
 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">;
 
 def int_hexagon_A2_absp :

 
 def int_hexagon_M4_vrmpyoh_s1 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
 
 def int_hexagon_C2_bitsset :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;
 
 def int_hexagon_M2_mpysip :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpysin :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin", [ImmArg<1>]>;
 
 def int_hexagon_A4_boundscheck :
 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;
 
 def int_hexagon_M5_vrmpybuu :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;
 
 def int_hexagon_C4_fastcorner9 :

 
 def int_hexagon_F2_conv_ud2df :
 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;
 
 def int_hexagon_A2_vnavgw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;
 
 def int_hexagon_S2_asl_i_r_acc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [ImmArg<2>]>;
 
 def int_hexagon_S4_subi_lsr_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_S2_vzxthw :
 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;
 
 def int_hexagon_F2_sfadd :
 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">;
 
 def int_hexagon_A2_sub :

 
 def int_hexagon_S2_insert :
 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">;
 
 def int_hexagon_S2_packhl :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;
 
 def int_hexagon_A4_vcmpwgti :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [ImmArg<1>]>;
 
 def int_hexagon_A2_vavguwr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;
 
 def int_hexagon_S2_asl_r_r_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
 
 def int_hexagon_A2_svsubhs :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;
 
 def int_hexagon_A2_addh_l16_hl :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
 
 def int_hexagon_M4_and_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;
 
 def int_hexagon_F2_conv_d2df :
 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;
 
 def int_hexagon_C2_cmpgtui :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [ImmArg<1>]>;
 
 def int_hexagon_A2_vconj :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;
 
 def int_hexagon_S2_lsr_r_vw :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
 
 def int_hexagon_S2_lsr_r_vh :

 
 def int_hexagon_C2_any8 :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;
 
 def int_hexagon_S2_togglebit_r :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;
 
 def int_hexagon_S2_togglebit_i :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [ImmArg<1>]>;
 
 def int_hexagon_F2_conv_uw2sf :
 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
 
 def int_hexagon_S2_vsathb_nopack :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
 
 def int_hexagon_M2_cmacs_s0 :

 
 def int_hexagon_C4_or_andn :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;
 
 def int_hexagon_S2_asl_r_r_nac :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
 
 def int_hexagon_S2_asl_i_p_acc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [ImmArg<2>]>;
 
 def int_hexagon_A4_vcmpwgtui :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [ImmArg<1>]>;
 
 def int_hexagon_M4_vrmpyoh_acc_s0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
 
 def int_hexagon_M4_vrmpyoh_acc_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
 
 def int_hexagon_A4_vrmaxh :

 
 def int_hexagon_M2_vrcmacr_s0c :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
 
 def int_hexagon_A2_vavgwcr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;
 
 def int_hexagon_S2_asl_i_p_xacc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [ImmArg<2>]>;
 
 def int_hexagon_A4_vrmaxw :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;
 
 def int_hexagon_A2_vnavghr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;
 
 def int_hexagon_M4_cmpyi_wh :
 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
 
 def int_hexagon_A2_tfrsi :
-Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi">;
+Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [ImmArg<0>]>;
 
 def int_hexagon_S2_asr_i_r_acc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [ImmArg<2>]>;
 
 def int_hexagon_A2_svnavgh :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;
 
 def int_hexagon_S2_lsr_i_r :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [ImmArg<1>]>;
 
 def int_hexagon_M2_vmac2 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;
 
 def int_hexagon_A4_vcmphgtui :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [ImmArg<1>]>;
 
 def int_hexagon_A2_svavgh :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;
 
 def int_hexagon_M4_vrmpyeh_acc_s0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
 
 def int_hexagon_M4_vrmpyeh_acc_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
 
 def int_hexagon_S2_lsr_i_p :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [ImmArg<1>]>;
 
 def int_hexagon_A2_combine_hl :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;
 
 def int_hexagon_M2_mpy_up :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;
 
 def int_hexagon_A2_combine_hh :

 
 def int_hexagon_S2_lsl_r_r_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
 
 def int_hexagon_M2_mmpyul_rs0 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
 
 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_r_p_nac :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
 
 def int_hexagon_C2_cmplt :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;
 
 def int_hexagon_M2_cmacr_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;
 
 def int_hexagon_M4_or_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;
 
 def int_hexagon_M4_mpyrr_addi :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [ImmArg<0>]>;
 
 def int_hexagon_S4_or_andi :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpy_sat_hl_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
 
 def int_hexagon_M2_mpy_sat_hl_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
 
 def int_hexagon_M4_mpyrr_addr :

 
 def int_hexagon_M2_mpy_rnd_hl_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
 
 def int_hexagon_F2_sffms_lib :
 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">;
 
 def int_hexagon_C4_cmpneqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [ImmArg<1>]>;
 
 def int_hexagon_M4_and_xor :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;
 
 def int_hexagon_A2_sat :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;
 
 def int_hexagon_M2_mpyd_nac_lh_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
 
 def int_hexagon_M2_mpyd_nac_lh_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
 
 def int_hexagon_A2_addsat :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;
 
 def int_hexagon_A2_svavghs :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;
 
 def int_hexagon_A2_vrsadub_acc :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
 
 def int_hexagon_C2_bitsclri :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [ImmArg<1>]>;
 
 def int_hexagon_A2_subh_h16_sat_hh :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
 
 def int_hexagon_A2_subh_h16_sat_hl :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
 
 def int_hexagon_M2_mmaculs_rs0 :

 
 def int_hexagon_C2_vmux :
 Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;
 
 def int_hexagon_S2_parityp :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;
 
 def int_hexagon_S2_lsr_i_p_and :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [ImmArg<2>]>;
 
 def int_hexagon_S2_asr_i_r_or :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpyu_nac_ll_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
 
 def int_hexagon_M2_mpyu_nac_ll_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
 
 def int_hexagon_F2_sfcmpeq :

 
 def int_hexagon_M2_cnacsc_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
 
 def int_hexagon_M2_cnacsc_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
 
 def int_hexagon_S4_subaddi :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpyud_nac_hl_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
 
 def int_hexagon_M2_mpyud_nac_hl_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
 
 def int_hexagon_S5_vasrhrnd_goodsyntax :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [ImmArg<1>]>;
 
 def int_hexagon_S2_tstbit_r :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;
 
 def int_hexagon_S4_vrcrotate :
-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate">;
+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [ImmArg<2>]>;
 
 def int_hexagon_M2_mmachs_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;
 
 def int_hexagon_M2_mmachs_s0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;
 
 def int_hexagon_S2_tstbit_i :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpy_up_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
 
 def int_hexagon_S2_extractu_rp :
 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;
 
 def int_hexagon_M2_mmpyuh_rs0 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
 
 def int_hexagon_S2_lsr_i_vw :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpy_rnd_ll_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
 
 def int_hexagon_M2_mpy_rnd_ll_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
 
 def int_hexagon_M4_or_or :

 
 def int_hexagon_F2_conv_w2df :
 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;
 
 def int_hexagon_A2_subh_l16_sat_hl :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
 
 def int_hexagon_C2_cmpeqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_r_and :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [ImmArg<2>]>;
 
 def int_hexagon_S2_vcnegh :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;
 
 def int_hexagon_A4_vcmpweqi :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [ImmArg<1>]>;
 
 def int_hexagon_M2_vdmpyrs_s0 :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
 
 def int_hexagon_M2_vdmpyrs_s1 :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
 
 def int_hexagon_M4_xor_xacc :

 
 def int_hexagon_S2_asl_r_r_acc :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
 
 def int_hexagon_S2_cl0p :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;
 
 def int_hexagon_S2_valignib :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [ImmArg<2>]>;
 
 def int_hexagon_F2_sffixupd :
 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">;
 
 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
 
 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :

 
 def int_hexagon_M2_dpmpyuu_nac_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
 
 def int_hexagon_M2_mmpyul_rs1 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
 
 def int_hexagon_S4_ntstbit_i :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [ImmArg<1>]>   ;
 
 def int_hexagon_F2_sffixupr :
 Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">;
 
 def int_hexagon_S2_asr_r_p_xor :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
 
 def int_hexagon_M2_mpyud_acc_hl_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
 
 def int_hexagon_M2_mpyud_acc_hl_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
 
 def int_hexagon_A2_vcmphgtu :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;
 
 def int_hexagon_C2_andn :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;
 
 def int_hexagon_M2_vmpy2s_s0pack :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
 
 def int_hexagon_S4_addaddi :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpyd_acc_ll_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
 
 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
 
 def int_hexagon_A4_rcmpeqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [ImmArg<1>]>;
 
 def int_hexagon_M4_xor_and :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;
 
 def int_hexagon_S2_asl_i_p_and :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [ImmArg<2>]>;
 
 def int_hexagon_M2_mmpyuh_rs1 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
 
 def int_hexagon_S2_asr_r_r_or :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
 
 def int_hexagon_A4_round_ri :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [ImmArg<1>]>;
 
 def int_hexagon_A2_max :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;
 
 def int_hexagon_A4_round_rr :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;
 
 def int_hexagon_A4_combineii :
-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii">;
+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii", [ImmArg<0>, ImmArg<1>]>;
 
 def int_hexagon_A4_combineir :
-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir">;
+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [ImmArg<0>]>;
 
 def int_hexagon_C4_and_orn :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;
 
 def int_hexagon_M5_vmacbuu :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;
 
 def int_hexagon_A4_rcmpeq :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;
 
 def int_hexagon_M4_cmpyr_whc :
 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
 
 def int_hexagon_S2_lsr_i_r_acc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [ImmArg<2>]>;
 
 def int_hexagon_S2_vzxtbh :
 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;
 
 def int_hexagon_M2_mmacuhs_rs1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
 
 def int_hexagon_S2_asr_r_r_sat :

 
 def int_hexagon_M2_cmpyi_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
 
 def int_hexagon_S2_asl_r_p_or :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
 
 def int_hexagon_S4_ori_asl_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_C4_nbitsset :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;
 
 def int_hexagon_M2_mpyu_acc_hh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
 
 def int_hexagon_M2_mpyu_acc_hh_s0 :

 
 def int_hexagon_M2_mpyd_acc_hh_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
 
 def int_hexagon_M2_mpyd_acc_hh_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
 
 def int_hexagon_F2_sfimm_p :
-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p">;
+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [ImmArg<0>]>;
 
 def int_hexagon_F2_sfimm_n :
-Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n">;
+Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [ImmArg<0>]>;
 
 def int_hexagon_M4_cmpyr_wh :
 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
 
 def int_hexagon_S2_lsl_r_p_and :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
 
 def int_hexagon_A2_vavgub :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;
 
 def int_hexagon_F2_conv_d2sf :
 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;
 
 def int_hexagon_A2_vavguh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;
 
 def int_hexagon_A4_cmpbeqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [ImmArg<1>]>;
 
 def int_hexagon_F2_sfcmpuo :
 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">;
 
 def int_hexagon_A2_vavguw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;
 
 def int_hexagon_S2_asr_i_p_nac :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [ImmArg<2>]>;
 
 def int_hexagon_S2_vsatwh_nopack :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
 
 def int_hexagon_M2_mpyd_hh_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
 
 def int_hexagon_M2_mpyd_hh_s1 :

 
 def int_hexagon_M4_or_andn :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;
 
 def int_hexagon_A2_minp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;
 
 def int_hexagon_S4_or_andix :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpy_rnd_lh_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
 
 def int_hexagon_M2_mpy_rnd_lh_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
 
 def int_hexagon_M2_mmpyuh_s0 :

 
 def int_hexagon_S4_extract_rp :
 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;
 
 def int_hexagon_S2_lsl_r_r_or :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
 
 def int_hexagon_C4_cmplteui :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [ImmArg<1>]>;
 
 def int_hexagon_S4_addi_lsr_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_A4_tfrcpp :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">;
 
 def int_hexagon_S2_asr_i_svw_trun :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [ImmArg<1>]>;
 
 def int_hexagon_A4_cmphgti :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [ImmArg<1>]>;
 
 def int_hexagon_A4_vrminh :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;
 
 def int_hexagon_A4_vrminw :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;
 
 def int_hexagon_A4_cmphgtu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;
 
 def int_hexagon_S2_insertp_rp :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;
 
 def int_hexagon_A2_vnavghcr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;
 
 def int_hexagon_S4_subi_asl_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_S2_lsl_r_vh :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
 
 def int_hexagon_M2_mpy_hh_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
 
 def int_hexagon_A2_vsubws :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;
 
 def int_hexagon_A2_sath :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;
 
 def int_hexagon_S2_asl_r_p_xor :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
 
 def int_hexagon_A2_satb :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;
 
 def int_hexagon_C2_cmpltu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;
 
 def int_hexagon_S2_insertp :
-Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp">;
+Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [ImmArg<2>, ImmArg<3>]>;
 
 def int_hexagon_M2_mpyd_rnd_ll_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
 
 def int_hexagon_M2_mpyd_rnd_ll_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
 
 def int_hexagon_S2_lsr_i_p_nac :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [ImmArg<2>]>;
 
 def int_hexagon_S2_extractup_rp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;
 
 def int_hexagon_S4_vxaddsubw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;
 
 def int_hexagon_S4_vxaddsubh :

 
 def int_hexagon_M2_cmpyr_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
 
 def int_hexagon_M2_dpmpyss_rnd_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
 
 def int_hexagon_C2_muxri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [ImmArg<1>]>;
 
 def int_hexagon_M2_vmac2es_s0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
 
 def int_hexagon_M2_vmac2es_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
 
 def int_hexagon_C2_pxfer_map :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;
 
 def int_hexagon_M2_mpyu_lh_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
 
 def int_hexagon_M2_mpyu_lh_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
 
 def int_hexagon_S2_asl_i_r_or :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpyd_acc_hl_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
 
 def int_hexagon_M2_mpyd_acc_hl_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
 
 def int_hexagon_S2_asr_r_p_nac :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
 
 def int_hexagon_A2_vaddw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;
 
 def int_hexagon_S2_asr_i_r_and :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [ImmArg<2>]>;
 
 def int_hexagon_A2_vaddh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;
 
 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
 
 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
 
 def int_hexagon_C2_cmpeqp :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;
 
 def int_hexagon_M4_mpyri_addi :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_A2_not :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;
 
 def int_hexagon_S4_andi_lsr_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_M2_macsip :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [ImmArg<2>]>;
 
 def int_hexagon_A2_tfrcrr :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">;
 
 def int_hexagon_M2_macsin :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [ImmArg<2>]>;
 
 def int_hexagon_C2_orn :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;
 
 def int_hexagon_M4_and_andn :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;
 
 def int_hexagon_F2_sfmpy :

 
 def int_hexagon_M2_vrcmpys_acc_s1 :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
 
 def int_hexagon_F2_dfcmpge :
 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">;
 
 def int_hexagon_M2_accii :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [ImmArg<2>]>;
 
 def int_hexagon_A5_vaddhubs :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;
 
 def int_hexagon_A2_vmaxw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;
 
 def int_hexagon_A2_vmaxb :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;
 
 def int_hexagon_A2_vmaxh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;
 
 def int_hexagon_S2_vsxthw :
 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;
 
 def int_hexagon_S4_andi_asl_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_S2_asl_i_p_nac :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [ImmArg<2>]>;
 
 def int_hexagon_S2_lsl_r_p_xor :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
 
 def int_hexagon_C2_cmpgt :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;
 
 def int_hexagon_F2_conv_df2d_chop :

 
 def int_hexagon_M2_mpyud_acc_lh_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
 
 def int_hexagon_M4_xor_andn :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;
 
 def int_hexagon_S2_addasl_rrri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [ImmArg<2>]>;
 
 def int_hexagon_M5_vdmpybsu :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;
 
 def int_hexagon_M2_mpyu_nac_hh_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
 
 def int_hexagon_M2_mpyu_nac_hh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
 
 def int_hexagon_A2_addi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [ImmArg<1>]>;
 
 def int_hexagon_A2_addp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;
 
 def int_hexagon_M2_vmpy2s_s1pack :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
 
 def int_hexagon_S4_clbpnorm :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;
 
 def int_hexagon_A4_round_rr_sat :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;
 
 def int_hexagon_M2_nacci :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;
 
 def int_hexagon_S2_shuffeh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;
 
 def int_hexagon_S2_lsr_i_r_and :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [ImmArg<2>]>;
 
 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
 
 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
 
 def int_hexagon_F2_conv_sf2uw :

 
 def int_hexagon_C2_and :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;
 
 def int_hexagon_S5_popcountp :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;
 
 def int_hexagon_S4_extractp :
-Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp">;
+Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [ImmArg<1>, ImmArg<2>]>;
 
 def int_hexagon_S2_cl0 :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;
 
 def int_hexagon_A4_vcmpbgti :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [ImmArg<1>]>;
 
 def int_hexagon_M2_mmacls_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;
 
 def int_hexagon_M2_mmacls_s0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;
 
 def int_hexagon_C4_cmpneq :

 
 def int_hexagon_M2_maci :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;
 
 def int_hexagon_A2_vmaxuh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;
 
 def int_hexagon_A4_bitspliti :
-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti">;
+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [ImmArg<1>]>;
 
 def int_hexagon_A2_vmaxub :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;
 
 def int_hexagon_M2_mpyud_hh_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
 
 def int_hexagon_M2_mpyud_hh_s1 :

 
 def int_hexagon_F2_conv_sf2d :
 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;
 
 def int_hexagon_S2_asr_r_r_nac :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
 
 def int_hexagon_F2_dfimm_n :
-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n">;
+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [ImmArg<0>]>;
 
 def int_hexagon_A4_cmphgt :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;
 
 def int_hexagon_F2_dfimm_p :
-Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p">;
+Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [ImmArg<0>]>;
 
 def int_hexagon_M2_mpyud_acc_lh_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
 
 def int_hexagon_M2_vcmpy_s1_sat_r :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
 
 def int_hexagon_M4_mpyri_addr_u2 :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [ImmArg<1>]>;
 
 def int_hexagon_M2_vcmpy_s1_sat_i :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
 
 def int_hexagon_S2_lsl_r_p_nac :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
 
 def int_hexagon_M5_vrmacbuu :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;
 
 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [ImmArg<1>]>;
 
 def int_hexagon_S2_vspliceib :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [ImmArg<2>]>;
 
 def int_hexagon_M2_dpmpyss_acc_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
 
 def int_hexagon_M2_cnacs_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;
 
 def int_hexagon_M2_cnacs_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;
 
 def int_hexagon_A2_maxu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;
 
 def int_hexagon_A2_maxp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;
 
 def int_hexagon_A2_andir :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [ImmArg<1>]>;
 
 def int_hexagon_F2_sfrecipa :
 Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">;
 
 def int_hexagon_A2_combineii :
-Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii">;
+Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [ImmArg<0>, ImmArg<1>]>;
 
 def int_hexagon_A4_orn :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;
 
 def int_hexagon_A4_cmpbgtui :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_r_r_or :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
 
 def int_hexagon_A4_vcmpbeqi :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsl_r_r :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;
 
 def int_hexagon_S2_lsl_r_p :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;
 
 def int_hexagon_A2_or :

 
 def int_hexagon_A2_satub :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;
 
 def int_hexagon_M2_vrcmpys_s1 :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
 
 def int_hexagon_S4_or_ori :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [ImmArg<2>]>;
 
 def int_hexagon_C4_fastcorner9_not :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
 
 def int_hexagon_A2_tfrih :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [ImmArg<1>]>;
 
 def int_hexagon_A2_tfril :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [ImmArg<1>]>;
 
 def int_hexagon_M4_mpyri_addr :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [ImmArg<2>]>;
 
 def int_hexagon_S2_vtrunehb :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;
 
 def int_hexagon_A2_vabsw :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;
 
 def int_hexagon_A2_vabsh :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;
 
 def int_hexagon_F2_sfsub :
 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">;
 
 def int_hexagon_C2_muxii :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [ImmArg<1>, ImmArg<2>]>;
 
 def int_hexagon_C2_muxir :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [ImmArg<2>]>;
 
 def int_hexagon_A2_swiz :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;
 
 def int_hexagon_S2_asr_i_p_and :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [ImmArg<2>]>;
 
 def int_hexagon_M2_cmpyrsc_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
 
 def int_hexagon_M2_cmpyrsc_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
 
 def int_hexagon_A2_vraddub :

 
 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
 
 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
 
 def int_hexagon_S4_extract :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [ImmArg<1>, ImmArg<2>]>;
 
 def int_hexagon_A2_vcmpweq :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;
 
 def int_hexagon_M2_acci :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;
 
 def int_hexagon_S2_lsr_i_p_acc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [ImmArg<2>]>;
 
 def int_hexagon_S2_lsr_i_p_or :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [ImmArg<2>]>;
 
 def int_hexagon_F2_conv_ud2sf :
 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
 
 def int_hexagon_A2_tfr :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;
 
 def int_hexagon_S2_asr_i_p_or :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [ImmArg<2>]>;
 
 def int_hexagon_A2_subri :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [ImmArg<0>]>;
 
 def int_hexagon_A4_vrmaxuw :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;
 
 def int_hexagon_M5_vmpybuu :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;
 
 def int_hexagon_A4_vrmaxuh :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;
 
 def int_hexagon_S2_asl_i_vw :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [ImmArg<1>]>;
 
 def int_hexagon_A2_vavgw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;
 
 def int_hexagon_S2_brev :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;
 
 def int_hexagon_A2_vavgh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;
 
 def int_hexagon_S2_clrbit_i :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_vh :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_i_r_or :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [ImmArg<2>]>;
 
 def int_hexagon_S2_lsl_r_r_nac :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
 
 def int_hexagon_M2_mmpyl_rs1 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
 
 def int_hexagon_M2_mpyud_hl_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
 
 def int_hexagon_M2_mmpyl_s0 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
 
 def int_hexagon_M2_mmpyl_s1 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
 
 def int_hexagon_M2_naccii :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [ImmArg<2>]>;
 
 def int_hexagon_S2_vrndpackwhs :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
 
 def int_hexagon_S2_vtrunewh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;
 
 def int_hexagon_M2_dpmpyss_nac_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
 
 def int_hexagon_M2_mpyd_ll_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
 
 def int_hexagon_M2_mpyd_ll_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
 
 def int_hexagon_M4_mac_up_s1_sat :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
 
 def int_hexagon_S4_vrcrotate_acc :
-Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc">;
+Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [ImmArg<3>]>;
 
 def int_hexagon_F2_conv_uw2df :
 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;
 
 def int_hexagon_A2_vaddubs :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;
 
 def int_hexagon_S2_asr_r_r_acc :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
 
 def int_hexagon_A2_orir :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [ImmArg<1>]>;
 
 def int_hexagon_A2_andp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;
 
 def int_hexagon_S2_lfsp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;
 
 def int_hexagon_A2_min :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;
 
 def int_hexagon_M2_mpysmi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [ImmArg<1>]>;
 
 def int_hexagon_M2_vcmpy_s0_sat_r :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
 
 def int_hexagon_M2_mpyu_acc_ll_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
 
 def int_hexagon_M2_mpyu_acc_ll_s0 :

 
 def int_hexagon_M2_mpyd_lh_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
 
 def int_hexagon_F2_conv_df2w :
 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;
 
 def int_hexagon_S5_asrhub_sat :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_r_xacc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [ImmArg<2>]>;
 
 def int_hexagon_F2_conv_df2d :
 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;
 
 def int_hexagon_M2_mmaculs_s1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
 
 def int_hexagon_M2_mmaculs_s0 :

 
 def int_hexagon_A2_vavghr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;
 
 def int_hexagon_F2_sffma_sc :
 Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">;
 
 def int_hexagon_F2_dfclass :
-Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass">;
+Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [ImmArg<1>]>;
 
 def int_hexagon_F2_conv_df2ud :
 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;
 
 def int_hexagon_F2_conv_df2uw :
 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;
 
 def int_hexagon_M2_cmpyrs_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
 
 def int_hexagon_M2_cmpyrs_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
 
 def int_hexagon_C4_cmpltei :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [ImmArg<1>]>;
 
 def int_hexagon_C4_cmplteu :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;
 
 def int_hexagon_A2_vsubb_map :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;
 
 def int_hexagon_A2_subh_l16_ll :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
 
 def int_hexagon_S2_asr_i_r_rnd :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [ImmArg<1>]>;
 
 def int_hexagon_M2_vrmpy_s0 :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
 
 def int_hexagon_M2_mpyd_rnd_hh_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
 
 def int_hexagon_M2_mpyd_rnd_hh_s0 :

 
 def int_hexagon_M2_mpyud_hl_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
 
 def int_hexagon_M2_vrcmpyi_s0c :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
 
 def int_hexagon_S2_asr_i_p_rnd :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [ImmArg<1>]>;
 
 def int_hexagon_A2_addpsat :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;
 
 def int_hexagon_A2_svaddhs :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;
 
 def int_hexagon_S4_ori_lsr_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
 
 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
 
 def int_hexagon_A2_vminw :

 
 def int_hexagon_M2_mpyud_lh_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
 
 def int_hexagon_S2_asl_r_r_or :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
 
 def int_hexagon_S4_lsli :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [ImmArg<0>]>;
 
 def int_hexagon_S2_lsl_r_vw :
 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
 
 def int_hexagon_M2_mpy_hh_s1 :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
 
 def int_hexagon_M4_vrmpyeh_s0 :

 
 def int_hexagon_A4_cmpbeq :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;
 
 def int_hexagon_A2_negp :
 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;
 
 def int_hexagon_S2_asl_i_r_sat :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [ImmArg<1>]>;
 
 def int_hexagon_A2_addh_l16_sat_hl :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
 
 def int_hexagon_S2_vsatwuh :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;
 
 def int_hexagon_F2_dfcmpgt :
 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">;
 
 def int_hexagon_S2_svsathb :
 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;
 
 def int_hexagon_C2_cmpgtup :
 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;
 
 def int_hexagon_A4_cround_ri :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [ImmArg<1>]>;
 
 def int_hexagon_S4_clbpaddi :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [ImmArg<1>]>;
 
 def int_hexagon_A4_cround_rr :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;
 
 def int_hexagon_C2_mux :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;
 
 def int_hexagon_M2_dpmpyuu_s0 :

 
 def int_hexagon_A2_vminuh :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;
 
 def int_hexagon_A2_vminub :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;
 
 def int_hexagon_S2_extractu :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [ImmArg<1>, ImmArg<2>]>;
 
 def int_hexagon_A2_svsubh :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;
 
 def int_hexagon_S4_clbaddi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [ImmArg<1>]>;
 
 def int_hexagon_F2_sffms :
 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">;
 
 def int_hexagon_S2_vsxtbh :
 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;
 
 def int_hexagon_M2_mpyud_nac_ll_s1 :

 
 def int_hexagon_M2_mpy_acc_hh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
 
 def int_hexagon_M2_mpy_acc_hh_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
 
 def int_hexagon_S4_addi_asl_ri :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
 
 def int_hexagon_M2_mpyd_nac_hh_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
 
 def int_hexagon_M2_mpyd_nac_hh_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
 
 def int_hexagon_S2_asr_i_r_nac :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [ImmArg<2>]>;
 
 def int_hexagon_A4_cmpheqi :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_r_p_xor :
 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
 
 def int_hexagon_M2_mpy_acc_hl_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
 
 def int_hexagon_M2_mpy_acc_hl_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
 
 def int_hexagon_F2_conv_sf2ud_chop :
 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
 
 def int_hexagon_C2_cmpgeui :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
 
 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
 
 def int_hexagon_S2_asl_r_p_and :

 
 def int_hexagon_M2_mpyud_nac_lh_s1 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
 
 def int_hexagon_M2_mpyud_nac_lh_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
 
 def int_hexagon_A4_round_ri_sat :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [ImmArg<1>]>;
 
 def int_hexagon_M2_mpy_nac_hl_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
 
 def int_hexagon_M2_mpy_nac_hl_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
 
 def int_hexagon_A2_vavghcr :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;
 
 def int_hexagon_M2_mmacls_rs0 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
 
 def int_hexagon_M2_mmacls_rs1 :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
 
 def int_hexagon_M2_cmaci_s0 :
 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;
 
 def int_hexagon_S2_setbit_i :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [ImmArg<1>]>;
 
 def int_hexagon_S2_asl_i_p_or :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [ImmArg<2>]>;
 
 def int_hexagon_A4_andn :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;
 
 def int_hexagon_M5_vrmpybsu :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;
 
 def int_hexagon_S2_vrndpackwh :
 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;
 
 def int_hexagon_M2_vcmac_s0_sat_r :
 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
 
 def int_hexagon_A2_vmaxuw :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;
 
 def int_hexagon_C2_bitsclr :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;
 
 def int_hexagon_M2_xor_xacc :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;
 
 def int_hexagon_A4_vcmpbgtui :
-Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui">;
+Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [ImmArg<1>]>;
 
 def int_hexagon_A4_ornp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;
 
 def int_hexagon_A2_tfrpi :
-Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi">;
+Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [ImmArg<0>]>;
 
 def int_hexagon_C4_and_or :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;
 
 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
 
 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
 
 def int_hexagon_A2_subh_h16_sat_ll :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
 
 def int_hexagon_A2_subh_h16_sat_lh :
 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
 
 def int_hexagon_M2_vmpy2su_s1 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
 
 def int_hexagon_M2_vmpy2su_s0 :
 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
 
 def int_hexagon_S2_asr_i_p_acc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [ImmArg<2>]>;
 
 def int_hexagon_C4_nbitsclri :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_i_vh :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [ImmArg<1>]>;
 
 def int_hexagon_S2_lsr_i_p_xacc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [ImmArg<2>]>;
 
 // V55 Scalar Instructions.
 
 def int_hexagon_A5_ACS :
 Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">;
 
 // V60 Scalar Instructions.
 
 def int_hexagon_S6_rol_i_p_and :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_r_xacc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_r_and :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_r_acc :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_p_xacc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_p :
-Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p">;
+Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [ImmArg<1>]>;
 
 def int_hexagon_S6_rol_i_p_nac :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_p_acc :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_r_or :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_r :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [ImmArg<1>]>;
 
 def int_hexagon_S6_rol_i_r_nac :
-Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac">;
+Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [ImmArg<2>]>;
 
 def int_hexagon_S6_rol_i_p_or :
-Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or">;
+Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [ImmArg<2>]>;
 
 // V62 Scalar Instructions.
 
 def int_hexagon_S6_vtrunehb_ppp :
 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
 
 def int_hexagon_V6_ldntnt0 :
 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">;

 
 def int_hexagon_F2_dfadd :
 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">;
 
 def int_hexagon_M2_mnaci :
 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;
 
 def int_hexagon_S2_mask :
-Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask">;
+Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [ImmArg<0>, ImmArg<1>]>;
 
 // V60 HVX Instructions.
 
 def int_hexagon_V6_veqb_or :
 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;
 
 def int_hexagon_V6_veqb_or_128B :
 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;

 
 def int_hexagon_V6_vaddh_dv :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;
 
 def int_hexagon_V6_vaddh_dv_128B :
 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
 
 def int_hexagon_V6_vrmpybusi :
-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi">;
+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vrmpybusi_128B :
-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">;
+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vshufoh :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;
 
 def int_hexagon_V6_vshufoh_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
 
 def int_hexagon_V6_vasrwv :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;
 
 def int_hexagon_V6_vasrwv_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
 
 def int_hexagon_V6_vdmpyhsuisat :
 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
 
 def int_hexagon_V6_vdmpyhsuisat_128B :
 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
 
 def int_hexagon_V6_vrsadubi_acc :
-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc">;
+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [ImmArg<3>]>;
 
 def int_hexagon_V6_vrsadubi_acc_128B :
-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">;
+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [ImmArg<3>]>;
 
 def int_hexagon_V6_vnavgw :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;
 
 def int_hexagon_V6_vnavgw_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
 
 def int_hexagon_V6_vnavgh :

 
 def int_hexagon_V6_vsubhsat :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;
 
 def int_hexagon_V6_vsubhsat_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
 
 def int_hexagon_V6_vrmpyubi_acc :
-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">;
+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [ImmArg<3>]>;
 
 def int_hexagon_V6_vrmpyubi_acc_128B :
-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">;
+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [ImmArg<3>]>;
 
 def int_hexagon_V6_vabsw :
 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;
 
 def int_hexagon_V6_vabsw_128B :
 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;
 
 def int_hexagon_V6_vaddwsat_dv :

 
 def int_hexagon_V6_vmpybv_acc :
 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
 
 def int_hexagon_V6_vmpybv_acc_128B :
 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
 
 def int_hexagon_V6_vrsadubi :
-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi">;
+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vrsadubi_128B :
-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B">;
+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vdmpyhb_dv_acc :
 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
 
 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
 
 def int_hexagon_V6_vshufeh :

 
 def int_hexagon_V6_vaddbnq :
 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;
 
 def int_hexagon_V6_vaddbnq_128B :
 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
 
 def int_hexagon_V6_vlalignbi :
-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi">;
+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vlalignbi_128B :
-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B">;
+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vsatwh :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;
 
 def int_hexagon_V6_vsatwh_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
 
 def int_hexagon_V6_vgtuh :

 
 def int_hexagon_V6_veqh_and :
 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;
 
 def int_hexagon_V6_veqh_and_128B :
 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
 
 def int_hexagon_V6_valignbi :
-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi">;
+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [ImmArg<2>]>;
 
 def int_hexagon_V6_valignbi_128B :
-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B">;
+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vaddwsat :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;
 
 def int_hexagon_V6_vaddwsat_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
 
 def int_hexagon_V6_veqw_and :

 
 def int_hexagon_V6_vsubh :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;
 
 def int_hexagon_V6_vsubh_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;
 
 def int_hexagon_V6_vrmpyubi :
-Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi">;
+Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vrmpyubi_128B :
-Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">;
+Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vminw :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;
 
 def int_hexagon_V6_vminw_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;
 
 def int_hexagon_V6_vmpyubv_acc :

 
 def int_hexagon_V6_vsubuhw :
 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;
 
 def int_hexagon_V6_vsubuhw_128B :
 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
 
 def int_hexagon_V6_vrmpybusi_acc :
-Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">;
+Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [ImmArg<3>]>;
 
 def int_hexagon_V6_vrmpybusi_acc_128B :
-Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">;
+Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [ImmArg<3>]>;
 
 def int_hexagon_V6_vasrw :
 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;
 
 def int_hexagon_V6_vasrw_128B :
 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;
 
 def int_hexagon_V6_vasrh :

 
 def int_hexagon_V6_vlsrb :
 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;
 
 def int_hexagon_V6_vlsrb_128B :
 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
 
 def int_hexagon_V6_vlutvwhi :
-Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi">;
+Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vlutvwhi_128B :
-Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">;
+Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vaddububb_sat :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
 
 def int_hexagon_V6_vaddububb_sat_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
 
 def int_hexagon_V6_vsubbsat_dv :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
 
 def int_hexagon_V6_vsubbsat_dv_128B :
 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
 
 def int_hexagon_V6_ldtp0 :
 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">;
 
 def int_hexagon_V6_ldtp0_128B :
 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">;
 
 def int_hexagon_V6_vlutvvb_oracci :
-Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">;
+Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [ImmArg<3>]>;
 
 def int_hexagon_V6_vlutvvb_oracci_128B :
-Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">;
+Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [ImmArg<3>]>;
 
 def int_hexagon_V6_vsubuwsat_dv :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
 
 def int_hexagon_V6_vsubuwsat_dv_128B :
 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
 
 def int_hexagon_V6_ldpnt0 :

 
 def int_hexagon_V6_vasrwuhrndsat :
 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
 
 def int_hexagon_V6_vasrwuhrndsat_128B :
 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
 
 def int_hexagon_V6_vlutvvbi :
-Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi">;
+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [ImmArg<2>]>;
 
 def int_hexagon_V6_vlutvvbi_128B :
-Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">;
+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [ImmArg<2>]>;
 
 def int_hexagon_V6_vsubuwsat :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;
 
 def int_hexagon_V6_vsubuwsat_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
 
 def int_hexagon_V6_vaddbsat_dv :

 
 def int_hexagon_V6_ldcnp0 :
 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">;
 
 def int_hexagon_V6_ldcnp0_128B :
 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">;
 
 def int_hexagon_V6_vlutvwh_oracci :
-Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">;
+Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [ImmArg<3>]>;
 
 def int_hexagon_V6_vlutvwh_oracci_128B :
-Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">;
+Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [ImmArg<3>]>;
 
 def int_hexagon_V6_vsubbsat :
 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;
 
 def int_hexagon_V6_vsubbsat_128B :
 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
 
 // V65 HVX Instructions.