[CodeGen] Don't scavenge non-saved regs in exception throwing functions

[olista01]

Summary

Previously, LiveRegUnits was assuming that if a block has no successors
and does not return, then no registers are live at the end of it
(because the end of the block is unreachable). This was causing the
register scavenger to use callee-saved registers to materialise stack
frame addresses without saving them in the prologue. This would normally
be fine, because the end of the block is unreachable, but this is not
legal if the block ends by throwing a C++ exception. If this happens,
the scratch register will be modified, but its previous value won't be
preserved, so it doesn't get restored by the exception unwinder.

[efriedma]

LivePhysRegs had some related issues; see https://reviews.llvm.org/D42655 (and related discussion on https://reviews.llvm.org/D42509, which was reverted). Can we structure this code the same way?

lib/CodeGen/LiveRegUnits.cpp

127–128

Please restructure this so we aren't checking succ_empty(); that check will cause wrong results in general.

[efriedma]

lib/CodeGen/LiveRegUnits.cpp

136

Looks like this comment fell out of date?

[efriedma]

LGTM

lib/CodeGen/LiveRegUnits.cpp

void LiveRegUnits::addPristines(const MachineFunction &MF) {
   addCalleeSavedRegs(Pristine, MF);
   /// Remove the ones that are not saved/restored; they are pristine.
   for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
     Pristine.removeReg(Info.getReg());
   addUnits(Pristine.getBitVector());
 }
 
 void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
-  if (!MBB.succ_empty()) {
-    addPristines(MF);
-    // To get the live-outs we simply merge the live-ins of all successors.
-    for (const MachineBasicBlock *Succ : MBB.successors())
-      addBlockLiveIns(*this, *Succ);
-  } else if (MBB.isReturnBlock()) {
-    // For the return block: Add all callee saved registers.
+
+
+
+  if (MBB.isReturnBlock()) {
     const MachineFrameInfo &MFI = MF.getFrameInfo();
     if (MFI.isCalleeSavedInfoValid())
       addCalleeSavedRegs(*this, MF);
   }
 }
 
 void LiveRegUnits::addLiveIns(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
   addPristines(MF);
   addBlockLiveIns(*this, MBB);
 }

test/CodeGen/ARM/register-scavenger-exceptions.mir

+# RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s
+
+--- |
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "armv7--none-eabi"
+
+  define hidden void @_Z3foov(i32 %P0, ...) {
+  entry:
+    %V1 = alloca [4075 x i8], align 8
+    %tmp3 = alloca i8, i32 undef, align 8
+    unreachable
+  }
+
+  declare dso_local void @_Z3barv() noreturn
+
+...
+---
+# Check that the register scavenger does pick r5 (not preserved in prolog) for
+# materialising a stack frame address when the function ends in throwing an
+# exception.
+# CHECK: $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r10, killed $r11, killed $lr
+# CHECK-NOT: $r5
+name:            _Z3foov
+stack:
+  - { id: 0, name: V1, type: default, offset: 0, size: 5000, alignment: 8,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4080, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+  - { id: 1, name: tmp3, type: variable-sized, offset: 0, alignment: 1,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4112, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0.entry:
+
+    $r0 = MOVi 0, 14, $noreg, $noreg
+    $r1 = MOVi 0, 14, $noreg, $noreg
+    $r2 = MOVi 0, 14, $noreg, $noreg
+    $r3 = MOVi 0, 14, $noreg, $noreg
+    $r4 = MOVi 0, 14, $noreg, $noreg
+    STRi12 killed $lr, %stack.2, 0, 14, $noreg :: (store 4 into %stack.2)
+    BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp
+
+...