[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.

[craig.topper]

Summary

This fixes the case in PR35982 though as discussed there, it is probably not a complete fix.

[efriedma]

I guess this is fine; we do technically need to clobber MM* when we see emms, in case someone writes an emms between two MMX operations. But this doesn't solve the related issues with pre-RA scheduling or IR code movement, though, so I'd hesitate to say this fixes PR35982.

It's unfortunate that emms is so slow on Intel processors that it's impractical to insert automatically like we do for vzeroupper.

[craig.topper]

Agreed, I wouldn't close the bug for this. But it gets us closer to generating not broken code for more cases with low effort.

How can we fix the IR code movement issue?

[efriedma]

Assuming we don't insert emms implicitly, I'm not sure how to express the restriction at the IR level.

We could try to model the FP status register as "memory", somehow, and say every MMX operation writes to it, by marking them inaccessiblememonly or something like that. But it's not clear how you model the interaction between that, and FP operations which we don't model as reading/writing memory. Granted, if your MMX-using function doesn't contain any values of floating-point type, the result would mostly work in practice.

[craig.topper]

Can we approve this patch? I'll leave the bugzilla open. I'll also try to find out if we have any other failing tests internally that might be hitting the pre-RA or IR issue. I know we have other scheduling related bug arounds FP

[efriedma]

LGTM

llvm/trunk/lib/Target/X86/X86Instr3DNow.td

 defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>;
 defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>;
 defm PFRSQRT  : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>;
 defm PFSUB    : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>;
 defm PFSUBR   : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>;
 defm PI2FD    : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>;
 defm PMULHRW  : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
 
-let SchedRW = [WriteEMMS] in
+let SchedRW = [WriteEMMS],
+    Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
+            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
                    [(int_x86_mmx_femms)]>, TB;
 
 // PREFETCHWT1 is supported we want to use it for everything but T0.
 def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{
   return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1();
 }]>;
 

llvm/trunk/lib/Target/X86/X86InstrMMX.td

def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
                   [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
                   Sched<[WriteCvtI2PS.Folded]>;
 }
 
 //===----------------------------------------------------------------------===//
 // MMX EMMS Instruction
 //===----------------------------------------------------------------------===//
 
-let SchedRW = [WriteEMMS] in
+let SchedRW = [WriteEMMS],
+    Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
+            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
 def MMX_EMMS  : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
 
 //===----------------------------------------------------------------------===//
 // MMX Scalar Instructions
 //===----------------------------------------------------------------------===//
 
 // Data Transfer Instructions
 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),

llvm/trunk/test/CodeGen/X86/pr35982.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=false | FileCheck %s --check-prefixes=CHECK,NOPOST
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=true | FileCheck %s --check-prefixes=CHECK,POST
 
 define float @PR35982_emms(<1 x i64>) nounwind {
-; NOPOST-LABEL: PR35982_emms:
-; NOPOST:       # %bb.0:
-; NOPOST-NEXT:    pushl %ebp
-; NOPOST-NEXT:    movl %esp, %ebp
-; NOPOST-NEXT:    andl $-8, %esp
-; NOPOST-NEXT:    subl $16, %esp
-; NOPOST-NEXT:    movl 8(%ebp), %eax
-; NOPOST-NEXT:    movl 12(%ebp), %ecx
-; NOPOST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movq {{[0-9]+}}(%esp), %mm0
-; NOPOST-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
-; NOPOST-NEXT:    movd %mm0, %ecx
-; NOPOST-NEXT:    emms
-; NOPOST-NEXT:    movl %eax, (%esp)
-; NOPOST-NEXT:    fildl (%esp)
-; NOPOST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    fiaddl {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movl %ebp, %esp
-; NOPOST-NEXT:    popl %ebp
-; NOPOST-NEXT:    retl
-;
-; POST-LABEL: PR35982_emms:
-; POST:       # %bb.0:
-; POST-NEXT:    pushl %ebp
-; POST-NEXT:    movl %esp, %ebp
-; POST-NEXT:    andl $-8, %esp
-; POST-NEXT:    subl $16, %esp
-; POST-NEXT:    movl 8(%ebp), %eax
-; POST-NEXT:    movl 12(%ebp), %ecx
-; POST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; POST-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; POST-NEXT:    movq {{[0-9]+}}(%esp), %mm0
-; POST-NEXT:    emms
-; POST-NEXT:    movl %eax, (%esp)
-; POST-NEXT:    fildl (%esp)
-; POST-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
-; POST-NEXT:    movd %mm0, %ecx
-; POST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; POST-NEXT:    fiaddl {{[0-9]+}}(%esp)
-; POST-NEXT:    movl %ebp, %esp
-; POST-NEXT:    popl %ebp
-; POST-NEXT:    retl
+; CHECK-LABEL: PR35982_emms:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    andl $-8, %esp
+; CHECK-NEXT:    subl $16, %esp
+; CHECK-NEXT:    movl 8(%ebp), %eax
+; CHECK-NEXT:    movl 12(%ebp), %ecx
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movq {{[0-9]+}}(%esp), %mm0
+; CHECK-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
+; CHECK-NEXT:    movd %mm0, %ecx
+; CHECK-NEXT:    emms
+; CHECK-NEXT:    movl %eax, (%esp)
+; CHECK-NEXT:    fildl (%esp)
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fiaddl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ebp, %esp
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
   %2 = bitcast <1 x i64> %0 to <2 x i32>
   %3 = extractelement <2 x i32> %2, i32 0
   %4 = extractelement <1 x i64> %0, i32 0
   %5 = bitcast i64 %4 to x86_mmx
   %6 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %5, x86_mmx %5)
   %7 = bitcast x86_mmx %6 to <2 x i32>
   %8 = extractelement <2 x i32> %7, i32 0
   tail call void @llvm.x86.mmx.emms()
   %9 = sitofp i32 %3 to float
   %10 = sitofp i32 %8 to float
   %11 = fadd float %9, %10
   ret float %11
 }
 
 define float @PR35982_femms(<1 x i64>) nounwind {
-; NOPOST-LABEL: PR35982_femms:
-; NOPOST:       # %bb.0:
-; NOPOST-NEXT:    pushl %ebp
-; NOPOST-NEXT:    movl %esp, %ebp
-; NOPOST-NEXT:    andl $-8, %esp
-; NOPOST-NEXT:    subl $16, %esp
-; NOPOST-NEXT:    movl 8(%ebp), %eax
-; NOPOST-NEXT:    movl 12(%ebp), %ecx
-; NOPOST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movq {{[0-9]+}}(%esp), %mm0
-; NOPOST-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
-; NOPOST-NEXT:    movd %mm0, %ecx
-; NOPOST-NEXT:    femms
-; NOPOST-NEXT:    movl %eax, (%esp)
-; NOPOST-NEXT:    fildl (%esp)
-; NOPOST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    fiaddl {{[0-9]+}}(%esp)
-; NOPOST-NEXT:    movl %ebp, %esp
-; NOPOST-NEXT:    popl %ebp
-; NOPOST-NEXT:    retl
-;
-; POST-LABEL: PR35982_femms:
-; POST:       # %bb.0:
-; POST-NEXT:    pushl %ebp
-; POST-NEXT:    movl %esp, %ebp
-; POST-NEXT:    andl $-8, %esp
-; POST-NEXT:    subl $16, %esp
-; POST-NEXT:    movl 8(%ebp), %eax
-; POST-NEXT:    movl 12(%ebp), %ecx
-; POST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; POST-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; POST-NEXT:    movq {{[0-9]+}}(%esp), %mm0
-; POST-NEXT:    femms
-; POST-NEXT:    movl %eax, (%esp)
-; POST-NEXT:    fildl (%esp)
-; POST-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
-; POST-NEXT:    movd %mm0, %ecx
-; POST-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; POST-NEXT:    fiaddl {{[0-9]+}}(%esp)
-; POST-NEXT:    movl %ebp, %esp
-; POST-NEXT:    popl %ebp
-; POST-NEXT:    retl
+; CHECK-LABEL: PR35982_femms:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    andl $-8, %esp
+; CHECK-NEXT:    subl $16, %esp
+; CHECK-NEXT:    movl 8(%ebp), %eax
+; CHECK-NEXT:    movl 12(%ebp), %ecx
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movq {{[0-9]+}}(%esp), %mm0
+; CHECK-NEXT:    punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
+; CHECK-NEXT:    movd %mm0, %ecx
+; CHECK-NEXT:    femms
+; CHECK-NEXT:    movl %eax, (%esp)
+; CHECK-NEXT:    fildl (%esp)
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fiaddl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ebp, %esp
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
   %2 = bitcast <1 x i64> %0 to <2 x i32>
   %3 = extractelement <2 x i32> %2, i32 0
   %4 = extractelement <1 x i64> %0, i32 0
   %5 = bitcast i64 %4 to x86_mmx
   %6 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %5, x86_mmx %5)
   %7 = bitcast x86_mmx %6 to <2 x i32>
   %8 = extractelement <2 x i32> %7, i32 0
   tail call void @llvm.x86.mmx.femms()