[X86][BtVer2] Update the WriteLoad latency.

[andreadb]

Summary

r327630 introduced new write definitions for float/vector loads.
Before that revision, WriteLoad was used by both integer/float (scalar/vector) load. So, WriteLoad had to conservatively declare a latency to 5cy. That is because the load-to-use latency for float/vector load is 5cy.

Now that we have dedicated writes for float/vector loads, there is no reason why we should keep the latency of WriteLoad to 5cy. At the moment, WriteLoad is only used by scalar integer loads only; we can assume an optimstic 3cy latency for them.
This patch changes that latency from 5cy to 3cy, and regenerates the affected scheduling/mca tests.

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

273

Can we remove this FIXME?

[andreadb]

Removed FIXME.

[RKSimon]

LGTM - folded scalar loads already use the 3cy load latency.

lib/Target/X86/X86ScheduleBtVer2.td

 defm : X86WriteRes<WriteSHDrrcl,[JALU01], 4, [8], 7>;
 defm : X86WriteRes<WriteSHDmri, [JLAGU, JALU01], 9, [1, 22], 8>;
 defm : X86WriteRes<WriteSHDmrcl,[JLAGU, JALU01], 9, [1, 22], 8>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Loads, stores, and moves, not folded with other operations.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteLoad,    [JLAGU]> { let Latency = 5; }
+def : WriteRes<WriteLoad,    [JLAGU]> { let Latency = 3; }
 def : WriteRes<WriteStore,   [JSAGU]>;
 def : WriteRes<WriteStoreNT, [JSAGU]>;
 def : WriteRes<WriteMove,    [JALU01]>;
 
 // Load/store MXCSR.
 // FIXME: These are copy and pasted from WriteLoad/Store.
-def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 5; }
+def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 3; }
 def : WriteRes<WriteSTMXCSR, [JSAGU]>;
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.

test/CodeGen/X86/schedule-x86-64-shld.ll

 ; BDVER12-NEXT:    # kill: def $cl killed $cl killed $rcx
 ; BDVER12-NEXT:    shrq %cl, %rdi # sched: [1:0.50]
 ; BDVER12-NEXT:    orq %rax, %rdi # sched: [1:0.50]
 ; BDVER12-NEXT:    movq %rdi, {{.*}}(%rip) # sched: [1:1.00]
 ; BDVER12-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: lshift_mem_cl:
 ; BTVER2:       # %bb.0: # %entry
-; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    movq %rsi, %rcx # sched: [1:0.50]
 ; BTVER2-NEXT:    shlq %cl, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    negb %cl # sched: [1:0.50]
 ; BTVER2-NEXT:    # kill: def $cl killed $cl killed $rcx
 ; BTVER2-NEXT:    shrq %cl, %rdi # sched: [1:0.50]
 ; BTVER2-NEXT:    orq %rax, %rdi # sched: [1:0.50]
 ; BTVER2-NEXT:    movq %rdi, {{.*}}(%rip) # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]

 ; BDVER12-NEXT:    shrq $54, %rdi # sched: [1:0.50]
 ; BDVER12-NEXT:    shlq $10, %rax # sched: [1:0.50]
 ; BDVER12-NEXT:    orq %rax, %rdi # sched: [1:0.50]
 ; BDVER12-NEXT:    movq %rdi, {{.*}}(%rip) # sched: [1:1.00]
 ; BDVER12-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: lshift_mem:
 ; BTVER2:       # %bb.0: # %entry
-; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    shrq $54, %rdi # sched: [1:0.50]
 ; BTVER2-NEXT:    shlq $10, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    orq %rax, %rdi # sched: [1:0.50]
 ; BTVER2-NEXT:    movq %rdi, {{.*}}(%rip) # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 entry:
   %b = load i64, i64* @x
   %shl = shl i64 %b, 10

 ; BDVER12-NEXT:    shlq $10, %rdi # sched: [1:0.50]
 ; BDVER12-NEXT:    shrq $54, %rax # sched: [1:0.50]
 ; BDVER12-NEXT:    orq %rdi, %rax # sched: [1:0.50]
 ; BDVER12-NEXT:    movq %rax, {{.*}}(%rip) # sched: [1:1.00]
 ; BDVER12-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: lshift_mem_b:
 ; BTVER2:       # %bb.0: # %entry
-; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    shlq $10, %rdi # sched: [1:0.50]
 ; BTVER2-NEXT:    shrq $54, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    orq %rdi, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    movq %rax, {{.*}}(%rip) # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 entry:
   %a = load i64, i64* @x
   %shl = shl i64 %b, 10

 ; BDVER12:       # %bb.0: # %entry
 ; BDVER12-NEXT:    movq {{.*}}(%rip), %rax # sched: [5:0.50]
 ; BDVER12-NEXT:    shrdq $54, %rdi, %rax # sched: [4:3.00]
 ; BDVER12-NEXT:    movq %rax, {{.*}}(%rip) # sched: [1:1.00]
 ; BDVER12-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: lshift_mem_b_optsize:
 ; BTVER2:       # %bb.0: # %entry
-; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{.*}}(%rip), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    shrdq $54, %rdi, %rax # sched: [3:3.00]
 ; BTVER2-NEXT:    movq %rax, {{.*}}(%rip) # sched: [1:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 entry:
   %a = load i64, i64* @x
   %shl = shl i64 %b, 10
   %shr = lshr i64 %a, 54
   %or = or i64 %shr, %shl
   store i64 %or, i64* @x
   ret void
 }
 

test/CodeGen/X86/schedule-x86_32.ll

 ; BDVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    aaa # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_aaa:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
+; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    aaa # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aaa:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    aam # sched: [100:0.50]
 ; BDVER2-NEXT:    aam $16 # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_aam:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
+; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    aam # sched: [100:0.50]
 ; BTVER2-NEXT:    aam $16 # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aam:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    aas # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_aas:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
+; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    aas # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_aas:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    arpl %ax, (%ecx) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_arpl:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    arpl %ax, (%ecx) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_arpl:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]

 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_bound:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    pushl %esi # sched: [1:1.00]
 ; BTVER2-NEXT:    .cfi_def_cfa_offset 8
 ; BTVER2-NEXT:    .cfi_offset %esi, -8
 ; BTVER2-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %esi # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %esi # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    bound %ax, (%esi) # sched: [100:0.50]
 ; BTVER2-NEXT:    bound %ecx, (%edx) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
-; BTVER2-NEXT:    popl %esi # sched: [5:1.00]
+; BTVER2-NEXT:    popl %esi # sched: [3:1.00]
 ; BTVER2-NEXT:    .cfi_def_cfa_offset 4
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_bound:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    pushl %esi # sched: [1:0.50]
 ; ZNVER1-NEXT:    .cfi_def_cfa_offset 8
 ; ZNVER1-NEXT:    .cfi_offset %esi, -8

 ; BDVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    daa # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_daa:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
+; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    daa # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_daa:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]

 ; BDVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    das # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_das:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
+; BTVER2-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    das # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_das:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]

 ; BDVER2-NEXT:    decw %ax # sched: [1:0.50]
 ; BDVER2-NEXT:    decw (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_dec16:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    decw %ax # sched: [1:0.50]
 ; BTVER2-NEXT:    decw (%ecx) # sched: [5:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dec16:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    decl %eax # sched: [1:0.50]
 ; BDVER2-NEXT:    decl (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_dec32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    decl %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    decl (%ecx) # sched: [5:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dec32:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    incw %ax # sched: [1:0.50]
 ; BDVER2-NEXT:    incw (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_inc16:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    incw %ax # sched: [1:0.50]
 ; BTVER2-NEXT:    incw (%ecx) # sched: [5:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_inc16:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    incl %eax # sched: [1:0.50]
 ; BDVER2-NEXT:    incl (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_inc32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    incl %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    incl (%ecx) # sched: [5:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_inc32:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    # sched: [1:1.00]
 ; BDVER2-NEXT:    pushw $7 # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_pop_push_16:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popw %ax # sched: [5:1.00]
-; BTVER2-NEXT:    popw (%ecx) # sched: [6:1.00]
+; BTVER2-NEXT:    popw %ax # sched: [3:1.00]
+; BTVER2-NEXT:    popw (%ecx) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushw %ax # sched: [1:1.00]
-; BTVER2-NEXT:    pushw (%ecx) # sched: [6:1.00]
+; BTVER2-NEXT:    pushw (%ecx) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushw $4095 # imm = 0xFFF
 ; BTVER2-NEXT:    # sched: [1:1.00]
 ; BTVER2-NEXT:    pushw $7 # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push_16:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    pushl $4095 # imm = 0xFFF
 ; BDVER2-NEXT:    # sched: [1:1.00]
 ; BDVER2-NEXT:    pushl $7 # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_pop_push_32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popl %eax # sched: [5:1.00]
-; BTVER2-NEXT:    popl (%ecx) # sched: [6:1.00]
+; BTVER2-NEXT:    popl %eax # sched: [3:1.00]
+; BTVER2-NEXT:    popl (%ecx) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushl %eax # sched: [1:1.00]
-; BTVER2-NEXT:    pushl (%ecx) # sched: [6:1.00]
+; BTVER2-NEXT:    pushl (%ecx) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushl $4095 # imm = 0xFFF
 ; BTVER2-NEXT:    # sched: [1:1.00]
 ; BTVER2-NEXT:    pushl $7 # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push_32:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    pushal # sched: [1:1.00]
 ; BDVER2-NEXT:    pushfl # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_popa_popf_pusha_pushf:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popal # sched: [5:1.00]
-; BTVER2-NEXT:    popfl # sched: [5:1.00]
+; BTVER2-NEXT:    popal # sched: [3:1.00]
+; BTVER2-NEXT:    popfl # sched: [3:1.00]
 ; BTVER2-NEXT:    pushal # sched: [1:1.00]
 ; BTVER2-NEXT:    pushfl # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_popa_popf_pusha_pushf:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP

 ; BDVER2-NEXT:    xchgl %eax, %eax # sched: [1:1.00]
 ; BDVER2-NEXT:    xchgl %ecx, %eax # sched: [1:1.00]
 ; BDVER2-NEXT:    xchgl %eax, (%edx) # sched: [5:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_xchg_32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    xchgl %eax, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    xchgl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    xchgl %eax, (%edx) # sched: [4:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xchg_32:

test/CodeGen/X86/schedule-x86_64.ll

 ; BDVER2-NEXT:    divl (%rax) # sched: [18:14.00]
 ; BDVER2-NEXT:    divq %rcx # sched: [14:14.00]
 ; BDVER2-NEXT:    divq (%r10) # sched: [18:14.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_div:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [3:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    divb %dil # sched: [12:12.00]
 ; BTVER2-NEXT:    divb (%r8) # sched: [15:12.00]
 ; BTVER2-NEXT:    divw %si # sched: [17:17.00]
 ; BTVER2-NEXT:    divw (%r9) # sched: [20:17.00]
 ; BTVER2-NEXT:    divl %edx # sched: [25:25.00]
 ; BTVER2-NEXT:    divl (%rax) # sched: [28:25.00]
 ; BTVER2-NEXT:    divq %rcx # sched: [41:41.00]

 ; BDVER2-NEXT:    idivl (%rax) # sched: [18:25.00]
 ; BDVER2-NEXT:    idivq %rcx # sched: [14:14.00]
 ; BDVER2-NEXT:    idivq (%r10) # sched: [18:14.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_idiv:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [3:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    idivb %dil # sched: [12:12.00]
 ; BTVER2-NEXT:    idivb (%r8) # sched: [15:12.00]
 ; BTVER2-NEXT:    idivw %si # sched: [17:17.00]
 ; BTVER2-NEXT:    idivw (%r9) # sched: [20:17.00]
 ; BTVER2-NEXT:    idivl %edx # sched: [25:25.00]
 ; BTVER2-NEXT:    idivl (%rax) # sched: [28:25.00]
 ; BTVER2-NEXT:    idivq %rcx # sched: [41:41.00]

 ; BDVER2-NEXT:    mull (%rax) # sched: [8:1.00]
 ; BDVER2-NEXT:    mulq %rcx # sched: [6:4.00]
 ; BDVER2-NEXT:    mulq (%r10) # sched: [10:4.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_mul:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [3:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    mulb %dil # sched: [3:1.00]
 ; BTVER2-NEXT:    mulb (%r8) # sched: [6:1.00]
 ; BTVER2-NEXT:    mulw %si # sched: [3:1.00]
 ; BTVER2-NEXT:    mulw (%r9) # sched: [6:1.00]
 ; BTVER2-NEXT:    mull %edx # sched: [3:1.00]
 ; BTVER2-NEXT:    mull (%rax) # sched: [6:1.00]
 ; BTVER2-NEXT:    mulq %rcx # sched: [6:4.00]

 ; BDVER2-NEXT:    negl (%rax) # sched: [6:1.00]
 ; BDVER2-NEXT:    negq %rcx # sched: [1:0.50]
 ; BDVER2-NEXT:    negq (%r10) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_neg:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [3:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    negb %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    negb (%r8) # sched: [5:1.00]
 ; BTVER2-NEXT:    negw %si # sched: [1:0.50]
 ; BTVER2-NEXT:    negw (%r9) # sched: [5:1.00]
 ; BTVER2-NEXT:    negl %edx # sched: [1:0.50]
 ; BTVER2-NEXT:    negl (%rax) # sched: [5:1.00]
 ; BTVER2-NEXT:    negq %rcx # sched: [1:0.50]

 ; BDVER2-NEXT:    notl (%rax) # sched: [6:1.00]
 ; BDVER2-NEXT:    notq %rcx # sched: [1:0.50]
 ; BDVER2-NEXT:    notq (%r10) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_not:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [5:1.00]
-; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [5:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %r10 # sched: [3:1.00]
+; BTVER2-NEXT:    movq {{[0-9]+}}(%rsp), %rax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    notb %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    notb (%r8) # sched: [5:1.00]
 ; BTVER2-NEXT:    notw %si # sched: [1:0.50]
 ; BTVER2-NEXT:    notw (%r9) # sched: [5:1.00]
 ; BTVER2-NEXT:    notl %edx # sched: [1:0.50]
 ; BTVER2-NEXT:    notl (%rax) # sched: [5:1.00]
 ; BTVER2-NEXT:    notq %rcx # sched: [1:0.50]

 ; BDVER2-NEXT:    # sched: [1:1.00]
 ; BDVER2-NEXT:    pushw $7 # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_pop_push_16:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popw %ax # sched: [5:1.00]
-; BTVER2-NEXT:    popw (%rsi) # sched: [6:1.00]
+; BTVER2-NEXT:    popw %ax # sched: [3:1.00]
+; BTVER2-NEXT:    popw (%rsi) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushw %di # sched: [1:1.00]
-; BTVER2-NEXT:    pushw (%rsi) # sched: [6:1.00]
+; BTVER2-NEXT:    pushw (%rsi) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushw $4095 # imm = 0xFFF
 ; BTVER2-NEXT:    # sched: [1:1.00]
 ; BTVER2-NEXT:    pushw $7 # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push_16:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    # sched: [1:1.00]
 ; BDVER2-NEXT:    pushq $7 # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_pop_push_64:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popq %rax # sched: [5:1.00]
-; BTVER2-NEXT:    popq (%rsi) # sched: [6:1.00]
+; BTVER2-NEXT:    popq %rax # sched: [3:1.00]
+; BTVER2-NEXT:    popq (%rsi) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushq %rdi # sched: [1:1.00]
-; BTVER2-NEXT:    pushq (%rsi) # sched: [6:1.00]
+; BTVER2-NEXT:    pushq (%rsi) # sched: [4:1.00]
 ; BTVER2-NEXT:    pushq $4095 # imm = 0xFFF
 ; BTVER2-NEXT:    # sched: [1:1.00]
 ; BTVER2-NEXT:    pushq $7 # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pop_push_64:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    popfq # sched: [5:0.50]
 ; BDVER2-NEXT:    pushfq # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_popf_pushf:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    popfq # sched: [5:1.00]
+; BTVER2-NEXT:    popfq # sched: [3:1.00]
 ; BTVER2-NEXT:    pushfq # sched: [1:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_popf_pushf:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    popfq # sched: [8:0.50]

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    xlatb # sched: [6:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_xlat:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    xlatb # sched: [5:1.00]
+; BTVER2-NEXT:    xlatb # sched: [3:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_xlat:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    xlatb # sched: [100:0.25]
 ; ZNVER1-NEXT:    #NO_APP

test/CodeGen/X86/sse-schedule.ll

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]
 ; BDVER2-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [5:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_ldmxcsr:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; BTVER2-SSE-NEXT:    ldmxcsr -{{[0-9]+}}(%rsp) # sched: [5:1.00]
+; BTVER2-SSE-NEXT:    ldmxcsr -{{[0-9]+}}(%rsp) # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_ldmxcsr:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; BTVER2-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [5:1.00]
+; BTVER2-NEXT:    vldmxcsr -{{[0-9]+}}(%rsp) # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_ldmxcsr:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:0.50]
 ; ZNVER1-SSE-NEXT:    ldmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-NEXT:    prefetcht1 (%rdi) # sched: [5:0.50]
 ; BDVER2-NEXT:    prefetcht2 (%rdi) # sched: [5:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_prefetch:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    #APP
-; BTVER2-SSE-NEXT:    prefetchnta (%rdi) # sched: [5:1.00]
-; BTVER2-SSE-NEXT:    prefetcht0 (%rdi) # sched: [5:1.00]
-; BTVER2-SSE-NEXT:    prefetcht1 (%rdi) # sched: [5:1.00]
-; BTVER2-SSE-NEXT:    prefetcht2 (%rdi) # sched: [5:1.00]
+; BTVER2-SSE-NEXT:    prefetchnta (%rdi) # sched: [3:1.00]
+; BTVER2-SSE-NEXT:    prefetcht0 (%rdi) # sched: [3:1.00]
+; BTVER2-SSE-NEXT:    prefetcht1 (%rdi) # sched: [3:1.00]
+; BTVER2-SSE-NEXT:    prefetcht2 (%rdi) # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    #NO_APP
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_prefetch:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    prefetchnta (%rdi) # sched: [5:1.00]
-; BTVER2-NEXT:    prefetcht0 (%rdi) # sched: [5:1.00]
-; BTVER2-NEXT:    prefetcht1 (%rdi) # sched: [5:1.00]
-; BTVER2-NEXT:    prefetcht2 (%rdi) # sched: [5:1.00]
+; BTVER2-NEXT:    prefetchnta (%rdi) # sched: [3:1.00]
+; BTVER2-NEXT:    prefetcht0 (%rdi) # sched: [3:1.00]
+; BTVER2-NEXT:    prefetcht1 (%rdi) # sched: [3:1.00]
+; BTVER2-NEXT:    prefetcht2 (%rdi) # sched: [3:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_prefetch:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    #APP
 ; ZNVER1-SSE-NEXT:    prefetchnta (%rdi) # sched: [8:0.50]
 ; ZNVER1-SSE-NEXT:    prefetcht0 (%rdi) # sched: [8:0.50]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]
 ; BDVER2-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [5:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_stmxcsr:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    stmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; BTVER2-SSE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [5:1.00]
+; BTVER2-SSE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_stmxcsr:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; BTVER2-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_stmxcsr:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    stmxcsr -{{[0-9]+}}(%rsp) # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax # sched: [8:0.50]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

test/CodeGen/X86/sse2-schedule.ll

 ;
 ; BDVER2-LABEL: test_clflush:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    clflush (%rdi) # sched: [5:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_clflush:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    clflush (%rdi) # sched: [5:1.00]
+; BTVER2-SSE-NEXT:    clflush (%rdi) # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_clflush:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    clflush (%rdi) # sched: [5:1.00]
+; BTVER2-NEXT:    clflush (%rdi) # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_clflush:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    clflush (%rdi) # sched: [8:0.50]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;
 ; ZNVER1-LABEL: test_clflush:

test/CodeGen/X86/x87-schedule.ll

 ; BDVER2-NEXT:    fadd %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fadds (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    faddl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fadd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fadd %st(0), %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fadd %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fadds (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    faddl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    faddp %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fiadds (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fiaddl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_faddp_fiadd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    faddp %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    faddp %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fiadds (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fiaddl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    fbld (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    fbstp (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fbld_fbstp:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fbld (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    fbstp (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fbld_fbstp:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    fcom %st(3) # sched: [1:1.00]
 ; BDVER2-NEXT:    fcoms (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    fcoml (%eax) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fcom:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fcom %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fcom %st(3) # sched: [3:1.00]
 ; BTVER2-NEXT:    fcoms (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fcoml (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fcomps (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    fcompl (%eax) # sched: [6:1.00]
 ; BDVER2-NEXT:    fcompp # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fcomp_fcompp:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fcomp %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fcomp %st(3) # sched: [3:1.00]
 ; BTVER2-NEXT:    fcomps (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fcompl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    fcompp # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]

 ; BDVER2-NEXT:    fdiv %st(2) # sched: [9:9.50]
 ; BDVER2-NEXT:    fdivs (%ecx) # sched: [14:9.50]
 ; BDVER2-NEXT:    fdivl (%eax) # sched: [14:9.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fdiv:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fdiv %st(0), %st(1) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdiv %st(2) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdivs (%ecx) # sched: [24:19.00]
 ; BTVER2-NEXT:    fdivl (%eax) # sched: [24:19.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fdivp %st(2) # sched: [9:9.50]
 ; BDVER2-NEXT:    fidivs (%ecx) # sched: [14:9.50]
 ; BDVER2-NEXT:    fidivl (%eax) # sched: [14:9.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fdivp_fidiv:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fdivp %st(1) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdivp %st(2) # sched: [19:19.00]
 ; BTVER2-NEXT:    fidivs (%ecx) # sched: [24:19.00]
 ; BTVER2-NEXT:    fidivl (%eax) # sched: [24:19.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fdivr %st(2) # sched: [9:9.50]
 ; BDVER2-NEXT:    fdivrs (%ecx) # sched: [14:9.50]
 ; BDVER2-NEXT:    fdivrl (%eax) # sched: [14:9.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fdivr:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fdivr %st(0), %st(1) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdivr %st(2) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdivrs (%ecx) # sched: [24:19.00]
 ; BTVER2-NEXT:    fdivrl (%eax) # sched: [24:19.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fdivrp %st(2) # sched: [9:9.50]
 ; BDVER2-NEXT:    fidivrs (%ecx) # sched: [14:9.50]
 ; BDVER2-NEXT:    fidivrl (%eax) # sched: [14:9.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fdivrp_fidivr:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fdivrp %st(1) # sched: [19:19.00]
 ; BTVER2-NEXT:    fdivrp %st(2) # sched: [19:19.00]
 ; BTVER2-NEXT:    fidivrs (%ecx) # sched: [24:19.00]
 ; BTVER2-NEXT:    fidivrl (%eax) # sched: [24:19.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    ficoml (%eax) # sched: [6:1.00]
 ; BDVER2-NEXT:    ficomps (%ecx) # sched: [6:1.00]
 ; BDVER2-NEXT:    ficompl (%eax) # sched: [6:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_ficom:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    ficoms (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    ficoml (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    ficomps (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    ficompl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    filds (%edx) # sched: [5:0.50]
 ; BDVER2-NEXT:    fildl (%ecx) # sched: [5:0.50]
 ; BDVER2-NEXT:    fildll (%eax) # sched: [5:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fild:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
-; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    filds (%edx) # sched: [5:1.00]
-; BTVER2-NEXT:    fildl (%ecx) # sched: [5:1.00]
-; BTVER2-NEXT:    fildll (%eax) # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
+; BTVER2-NEXT:    #APP
+; BTVER2-NEXT:    filds (%edx) # sched: [3:1.00]
+; BTVER2-NEXT:    fildl (%ecx) # sched: [3:1.00]
+; BTVER2-NEXT:    fildll (%eax) # sched: [3:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fild:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50]

 ; BDVER2-NEXT:    fisttps (%edx) # sched: [1:1.00]
 ; BDVER2-NEXT:    fisttpl (%ecx) # sched: [1:1.00]
 ; BDVER2-NEXT:    fisttpll (%eax) # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fist_fistp_fisttp:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fists (%edx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fistl (%ecx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fistps (%edx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fistpl (%ecx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fistpll (%eax) # sched: [1:1.00]
 ; BTVER2-NEXT:    fisttps (%edx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fisttpl (%ecx) # sched: [1:1.00]

 ; BDVER2-NEXT:    flds (%edx) # sched: [5:0.50]
 ; BDVER2-NEXT:    fldl (%ecx) # sched: [5:0.50]
 ; BDVER2-NEXT:    fldt (%eax) # sched: [5:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fld:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fld %st(0) # sched: [1:0.50]
-; BTVER2-NEXT:    flds (%edx) # sched: [5:1.00]
-; BTVER2-NEXT:    fldl (%ecx) # sched: [5:1.00]
-; BTVER2-NEXT:    fldt (%eax) # sched: [5:1.00]
+; BTVER2-NEXT:    flds (%edx) # sched: [3:1.00]
+; BTVER2-NEXT:    fldl (%ecx) # sched: [3:1.00]
+; BTVER2-NEXT:    fldt (%eax) # sched: [3:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fld:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50]

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    fldcw (%eax) # sched: [5:0.50]
 ; BDVER2-NEXT:    fldenv (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fldcw_fldenv:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    fldcw (%eax) # sched: [5:1.00]
+; BTVER2-NEXT:    fldcw (%eax) # sched: [3:1.00]
 ; BTVER2-NEXT:    fldenv (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fldcw_fldenv:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
 ; ZNVER1-NEXT:    #APP

 ; BDVER2-NEXT:    fmul %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fmuls (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fmull (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fmul:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fmul %st(0), %st(1) # sched: [2:1.00]
 ; BTVER2-NEXT:    fmul %st(2) # sched: [2:1.00]
 ; BTVER2-NEXT:    fmuls (%ecx) # sched: [7:1.00]
 ; BTVER2-NEXT:    fmull (%eax) # sched: [7:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fmulp %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fimuls (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fimull (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fmulp_fimul:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fmulp %st(1) # sched: [2:1.00]
 ; BTVER2-NEXT:    fmulp %st(2) # sched: [2:1.00]
 ; BTVER2-NEXT:    fimuls (%ecx) # sched: [7:1.00]
 ; BTVER2-NEXT:    fimull (%eax) # sched: [7:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    frstor (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_frstor:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    frstor (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_frstor:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    wait # sched: [100:0.50]
 ; BDVER2-NEXT:    fnsave (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fsave:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    wait # sched: [100:0.50]
 ; BTVER2-NEXT:    fnsave (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fsave:
 ; ZNVER1:       # %bb.0:

 ; BDVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    fnsave (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fnsave:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fnsave (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnsave:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]

 ; BDVER2-NEXT:    fstpl (%edx) # sched: [1:1.00]
 ; BDVER2-NEXT:    fstpl (%ecx) # sched: [1:1.00]
 ; BDVER2-NEXT:    fstpt (%eax) # sched: [1:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fst_fstp:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fst %st(0) # sched: [1:0.50]
 ; BTVER2-NEXT:    fsts (%edx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fstl (%ecx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fstp %st(0) # sched: [1:0.50]
 ; BTVER2-NEXT:    fstpl (%edx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fstpl (%ecx) # sched: [1:1.00]
 ; BTVER2-NEXT:    fstpt (%eax) # sched: [1:1.00]

 ; BDVER2-NEXT:    fnstenv (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    wait # sched: [100:0.50]
 ; BDVER2-NEXT:    fnstsw (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fstcw_fstenv_fstsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    wait # sched: [100:0.50]
 ; BTVER2-NEXT:    fnstcw (%eax) # sched: [1:0.50]
 ; BTVER2-NEXT:    wait # sched: [100:0.50]
 ; BTVER2-NEXT:    fnstenv (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    wait # sched: [100:0.50]
 ; BTVER2-NEXT:    fnstsw (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP

 ; BDVER2-NEXT:    fnstcw (%eax) # sched: [1:0.50]
 ; BDVER2-NEXT:    fnstenv (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    fnstsw (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fnstcw_fnstenv_fnstsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fnstcw (%eax) # sched: [1:0.50]
 ; BTVER2-NEXT:    fnstenv (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    fnstsw (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnstcw_fnstenv_fnstsw:

 ; BDVER2-NEXT:    fsub %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fsubs (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fsubl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fsub:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsub %st(0), %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsub %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsubs (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fsubl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fsubp %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fisubs (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fisubl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fsubp_fisub:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsubp %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsubp %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fisubs (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fisubl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fsubr %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fsubrs (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fsubrl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fsubr:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsubr %st(0), %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsubr %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsubrs (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fsubrl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    fsubrp %st(2) # sched: [5:1.00]
 ; BDVER2-NEXT:    fisubrs (%ecx) # sched: [10:1.00]
 ; BDVER2-NEXT:    fisubrl (%eax) # sched: [10:1.00]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fsubrp_fisubr:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fsubrp %st(1) # sched: [3:1.00]
 ; BTVER2-NEXT:    fsubrp %st(2) # sched: [3:1.00]
 ; BTVER2-NEXT:    fisubrs (%ecx) # sched: [8:1.00]
 ; BTVER2-NEXT:    fisubrl (%eax) # sched: [8:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;

 ; BDVER2-NEXT:    #APP
 ; BDVER2-NEXT:    fxrstor (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    fxsave (%eax) # sched: [100:0.50]
 ; BDVER2-NEXT:    #NO_APP
 ; BDVER2-NEXT:    retl # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_fxrstor_fxsave:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
+; BTVER2-NEXT:    movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    #APP
 ; BTVER2-NEXT:    fxrstor (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    fxsave (%eax) # sched: [100:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fxrstor_fxsave:
 ; ZNVER1:       # %bb.0:

test/tools/llvm-mca/X86/BtVer2/resources-avx1.s

 # CHECK-NEXT:  2      4     2.00                        vhsubps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      9     2.00    *                   vhsubps (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  2      1     1.00                        vinsertf128 $1, %xmm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      6     1.00    *                   vinsertf128 $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vinsertps $1, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   vinsertps $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00    *                   vlddqu  (%rax), %xmm2
 # CHECK-NEXT:  1      5     1.00    *                   vlddqu  (%rax), %ymm2
-# CHECK-NEXT:  1      5     1.00    *      *      U     vldmxcsr  (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *      U     vldmxcsr  (%rax)
 # CHECK-NEXT:  1      1     1.00    *      *      U     vmaskmovdqu %xmm0, %xmm1
 # CHECK-NEXT:  1      6     1.00    *                   vmaskmovpd  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      6     2.00    *                   vmaskmovpd  (%rax), %ymm0, %ymm2
 # CHECK-NEXT:  1      6     2.00    *      *            vmaskmovpd  %xmm0, %xmm1, (%rax)
 # CHECK-NEXT:  2      6     2.00    *      *            vmaskmovpd  %ymm0, %ymm1, (%rax)
 # CHECK-NEXT:  1      6     1.00    *                   vmaskmovps  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      6     2.00    *                   vmaskmovps  (%rax), %ymm0, %ymm2
 # CHECK-NEXT:  1      6     2.00    *      *            vmaskmovps  %xmm0, %xmm1, (%rax)

test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -instruction-tables < %s | FileCheck %s
 
 prefetch    (%rax)
 prefetchw   (%rax)
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      5     1.00    *      *            prefetch  (%rax)
-# CHECK-NEXT:  1      5     1.00    *      *            prefetchw (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetch  (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetchw (%rax)
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0

test/tools/llvm-mca/X86/BtVer2/resources-sse1.s

 # CHECK-NEXT:  2      7     1.00                        cvttss2si %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        cvttss2si %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   cvttss2si (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   cvttss2si (%rax), %rcx
 # CHECK-NEXT:  1      19    19.00                       divps %xmm0, %xmm2
 # CHECK-NEXT:  1      24    19.00   *                   divps (%rax), %xmm2
 # CHECK-NEXT:  1      19    19.00                       divss %xmm0, %xmm2
 # CHECK-NEXT:  1      24    19.00   *                   divss (%rax), %xmm2
-# CHECK-NEXT:  1      5     1.00    *      *      U     ldmxcsr (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *      U     ldmxcsr (%rax)
 # CHECK-NEXT:  1      1     0.50    *      *      U     maskmovq  %mm0, %mm1
 # CHECK-NEXT:  1      2     1.00                        maxps %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   maxps (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        maxss %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   maxss (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        minps %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   minps (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        minss %xmm0, %xmm2

 # CHECK-NEXT:  1      6     1.00    *                   pmaxub  (%rax), %mm2
 # CHECK-NEXT:  1      1     0.50                        pminsw  %mm0, %mm2
 # CHECK-NEXT:  1      6     1.00    *                   pminsw  (%rax), %mm2
 # CHECK-NEXT:  1      1     0.50                        pminub  %mm0, %mm2
 # CHECK-NEXT:  1      6     1.00    *                   pminub  (%rax), %mm2
 # CHECK-NEXT:  1      3     1.00                        pmovmskb  %xmm0, %ecx
 # CHECK-NEXT:  1      2     1.00                        pmulhuw %mm0, %mm2
 # CHECK-NEXT:  1      7     1.00    *                   pmulhuw (%rax), %mm2
-# CHECK-NEXT:  1      5     1.00    *      *            prefetcht0  (%rax)
-# CHECK-NEXT:  1      5     1.00    *      *            prefetcht1  (%rax)
-# CHECK-NEXT:  1      5     1.00    *      *            prefetcht2  (%rax)
-# CHECK-NEXT:  1      5     1.00    *      *            prefetchnta (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetcht0  (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetcht1  (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetcht2  (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *            prefetchnta (%rax)
 # CHECK-NEXT:  1      2     0.50                        psadbw  %mm0, %mm2
 # CHECK-NEXT:  1      7     1.00    *                   psadbw  (%rax), %mm2
 # CHECK-NEXT:  1      1     0.50                        pshufw  $1, %mm0, %mm2
 # CHECK-NEXT:  1      6     1.00    *                   pshufw  $1, (%rax), %mm2
 # CHECK-NEXT:  1      2     1.00                        rcpps %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   rcpps (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        rcpss %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   rcpss (%rax), %xmm2

test/tools/llvm-mca/X86/BtVer2/resources-sse2.s

 # CHECK-NEXT:  1      3     1.00                        addpd %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   addpd (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        addsd %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   addsd (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        andnpd  %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   andnpd  (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        andpd %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   andpd (%rax), %xmm2
-# CHECK-NEXT:  1      5     1.00    *      *      U     clflush (%rax)
+# CHECK-NEXT:  1      3     1.00    *      *      U     clflush (%rax)
 # CHECK-NEXT:  1      2     1.00                        cmppd $0, %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   cmppd $0, (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        cmpsd $0, %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   cmpsd $0, (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        comisd  %xmm0, %xmm1
 # CHECK-NEXT:  1      8     1.00    *                   comisd  (%rax), %xmm1
 # CHECK-NEXT:  1      3     1.00                        cvtdq2pd  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   cvtdq2pd  (%rax), %xmm2

test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        xchgw %bx, %cx
 # CHECK-NEXT:  1      4     1.00    *      *            xchgw %ax, (%rbx)
 # CHECK-NEXT:  1      1     0.50                        xchgl %ebx, %eax
 # CHECK-NEXT:  1      1     0.50                        xchgl %ebx, %ecx
 # CHECK-NEXT:  1      4     1.00    *      *            xchgl %eax, (%rbx)
 # CHECK-NEXT:  1      1     0.50                        xchgq %rbx, %rax
 # CHECK-NEXT:  1      1     0.50                        xchgq %rbx, %rcx
 # CHECK-NEXT:  1      4     1.00    *      *            xchgq %rax, (%rbx)
-# CHECK-NEXT:  1      5     1.00    *                   xlatb
+# CHECK-NEXT:  1      3     1.00    *                   xlatb
 # CHECK-NEXT:  1      1     0.50                        xorb  $7, %al
 # CHECK-NEXT:  1      1     0.50                        xorb  $7, %dil
 # CHECK-NEXT:  1      5     1.00    *      *            xorb  $7, (%rax)
 # CHECK-NEXT:  1      1     0.50                        xorb  %sil, %dil
 # CHECK-NEXT:  1      5     1.00    *      *            xorb  %sil, (%rax)
 # CHECK-NEXT:  1      4     1.00    *                   xorb  (%rax), %dil
 # CHECK-NEXT:  1      1     0.50                        xorw  $511, %ax
 # CHECK-NEXT:  1      1     0.50                        xorw  $511, %di

test/tools/llvm-mca/X86/BtVer2/resources-x87.s

 # CHECK-NEXT:  1      19    19.00                 U     fdivrp  %st(2)
 # CHECK-NEXT:  1      24    19.00   *             U     fidivrs (%ecx)
 # CHECK-NEXT:  1      24    19.00   *             U     fidivrl (%eax)
 # CHECK-NEXT:  1      100   0.50                  U     ffree %st(0)
 # CHECK-NEXT:  1      8     1.00                  U     ficoms  (%ecx)
 # CHECK-NEXT:  1      8     1.00                  U     ficoml  (%eax)
 # CHECK-NEXT:  1      8     1.00                  U     ficomps (%ecx)
 # CHECK-NEXT:  1      8     1.00                  U     ficompl (%eax)
-# CHECK-NEXT:  1      5     1.00    *             U     filds (%edx)
-# CHECK-NEXT:  1      5     1.00    *             U     fildl (%ecx)
-# CHECK-NEXT:  1      5     1.00    *             U     fildll  (%eax)
+# CHECK-NEXT:  1      3     1.00    *             U     filds (%edx)
+# CHECK-NEXT:  1      3     1.00    *             U     fildl (%ecx)
+# CHECK-NEXT:  1      3     1.00    *             U     fildll  (%eax)
 # CHECK-NEXT:  1      100   0.50                  U     fincstp
 # CHECK-NEXT:  1      100   0.50                  U     fninit
 # CHECK-NEXT:  1      1     1.00           *      U     fists (%edx)
 # CHECK-NEXT:  1      1     1.00           *      U     fistl (%ecx)
 # CHECK-NEXT:  1      1     1.00           *      U     fistps  (%edx)
 # CHECK-NEXT:  1      1     1.00           *      U     fistpl  (%ecx)
 # CHECK-NEXT:  1      1     1.00           *      U     fistpll (%eax)
 # CHECK-NEXT:  1      1     1.00           *      U     fisttps (%edx)
 # CHECK-NEXT:  1      1     1.00           *      U     fisttpl (%ecx)
 # CHECK-NEXT:  1      1     1.00           *      U     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.50                  U     fld %st(0)
-# CHECK-NEXT:  1      5     1.00    *             U     flds  (%edx)
-# CHECK-NEXT:  1      5     1.00    *             U     fldl  (%ecx)
-# CHECK-NEXT:  1      5     1.00    *             U     fldt  (%eax)
-# CHECK-NEXT:  1      5     1.00    *             U     fldcw (%eax)
+# CHECK-NEXT:  1      3     1.00    *             U     flds  (%edx)
+# CHECK-NEXT:  1      3     1.00    *             U     fldl  (%ecx)
+# CHECK-NEXT:  1      3     1.00    *             U     fldt  (%eax)
+# CHECK-NEXT:  1      3     1.00    *             U     fldcw (%eax)
 # CHECK-NEXT:  1      100   0.50                  U     fldenv  (%eax)
 # CHECK-NEXT:  1      3     1.00                  U     fld1
 # CHECK-NEXT:  1      3     1.00                  U     fldl2e
 # CHECK-NEXT:  1      3     1.00                  U     fldl2t
 # CHECK-NEXT:  1      3     1.00                  U     fldlg2
 # CHECK-NEXT:  1      3     1.00                  U     fldln2
 # CHECK-NEXT:  1      3     1.00                  U     fldpi
 # CHECK-NEXT:  1      3     1.00                  U     fldz