[X86][BtVer2] Update latency of horizontal operations.

[andreadb]

Summary

On Jaguar, horizontal adds/subs have local forwarding disable.
That means, we pay a compulsory extra cycle of write-back stage, and the value is not available until the end of that stage.

This patch changes the latency of horizontal operations by adding an extra cycle. With this patch, latency numbers now match what is reported by perf.

I plan to send another patch to also 'fix' the latency of shuffle operations (on Jaguar, local forwarding is disabled for vector shuffles too).

[andreadb]

Added comments.

[andreadb]

Patch updated.

I moved the comment about the +1cy latency at the top of the tablegen file.
I then added a simpler +1cy latency comment on each modified line.

Hopefully this is more readable.

[RKSimon]

LGTM - this also matches what exegesis reports

lib/Target/X86/X86ScheduleBtVer2.td

 defm : JWriteResFpuPair<WriteAESIMC,      [JFPU0, JVIMUL], 2>;
 defm : JWriteResFpuPair<WriteAESKeyGen,   [JFPU0, JVIMUL], 2>;
 defm : JWriteResFpuPair<WriteAESDecEnc,   [JFPU01, JVALU, JFPU0, JVIMUL], 3, [1,1,1,1], 2>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Horizontal add/sub  instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-defm : JWriteResFpuPair<WriteFHAdd,         [JFPU0, JFPA], 3>;
-defm : JWriteResYMMPair<WriteFHAddY,        [JFPU0, JFPA], 3, [2,2], 2>;
-defm : JWriteResFpuPair<WritePHAdd,       [JFPU01, JVALU], 1>;
-defm : JWriteResFpuPair<WritePHAddX,      [JFPU01, JVALU], 1>;
+defm : JWriteResFpuPair<WriteFHAdd,         [JFPU0, JFPA], 4>;
+defm : JWriteResYMMPair<WriteFHAddY,        [JFPU0, JFPA], 4, [2,2], 2>;
+defm : JWriteResFpuPair<WritePHAdd,         [JFPU01, JVALU], 2>;
+defm : JWriteResFpuPair<WritePHAddX,        [JFPU01, JVALU], 2>;
 defm : X86WriteResPairUnsupported<WritePHAddY>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Carry-less multiplication instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResFpuPair<WriteCLMul,       [JFPU0, JVIMUL], 2>;
 

test/CodeGen/X86/avx-schedule.ll

 ; BDVER2-LABEL: test_haddpd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [11:2.00]
 ; BDVER2-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [16:2.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_haddpd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
+; BTVER2-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
+; BTVER2-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_haddpd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vhaddpd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vhaddpd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1)

 ; BDVER2-LABEL: test_haddps:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [11:2.00]
 ; BDVER2-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [16:2.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_haddps:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
+; BTVER2-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
+; BTVER2-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_haddps:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vhaddps %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vhaddps (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1)

 ; BDVER2-LABEL: test_hsubpd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [11:2.00]
 ; BDVER2-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [16:2.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_hsubpd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
+; BTVER2-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
+; BTVER2-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_hsubpd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vhsubpd %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vhsubpd (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)

 ; BDVER2-LABEL: test_hsubps:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [11:2.00]
 ; BDVER2-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [16:2.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_hsubps:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [8:2.00]
+; BTVER2-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
+; BTVER2-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_hsubps:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vhsubps %ymm1, %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    vhsubps (%rdi), %ymm0, %ymm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)

test/CodeGen/X86/mmx-schedule.ll

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phaddd %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phaddd (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phaddd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phaddd %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phaddd (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phaddd %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phaddd (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phaddd %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phaddd (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phaddsw %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phaddsw (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phaddsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phaddsw %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phaddsw (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phaddsw %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phaddsw (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddsw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phaddsw %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phaddsw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phaddw %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phaddw (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phaddw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phaddw %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phaddw (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phaddw %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phaddw (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phaddw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phaddw %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phaddw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phsubd %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phsubd (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phsubd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phsubd %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phsubd (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phsubd %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phsubd (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phsubd %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phsubd (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phsubsw %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phsubsw (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phsubsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phsubsw %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phsubsw (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phsubsw %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phsubsw (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubsw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phsubsw %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phsubsw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    phsubw %mm1, %mm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    phsubw (%rdi), %mm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_phsubw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    phsubw %mm1, %mm0 # sched: [1:0.50]
-; BTVER2-NEXT:    phsubw (%rdi), %mm0 # sched: [6:1.00]
+; BTVER2-NEXT:    phsubw %mm1, %mm0 # sched: [2:0.50]
+; BTVER2-NEXT:    phsubw (%rdi), %mm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    movq %mm0, %rax # sched: [4:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_phsubw:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    phsubw %mm1, %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    phsubw (%rdi), %mm0 # sched: [100:0.25]
 ; ZNVER1-NEXT:    movq %mm0, %rax # sched: [2:1.00]

test/CodeGen/X86/sse3-schedule.ll

 ; BDVER2-LABEL: test_haddpd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
 ; BDVER2-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_haddpd:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    haddpd %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-SSE-NEXT:    haddpd (%rdi), %xmm0 # sched: [8:1.00]
+; BTVER2-SSE-NEXT:    haddpd %xmm1, %xmm0 # sched: [4:1.00]
+; BTVER2-SSE-NEXT:    haddpd (%rdi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_haddpd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vhaddpd %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; BTVER2-NEXT:    vhaddpd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_haddpd:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    haddpd %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    haddpd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_haddps:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
 ; BDVER2-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_haddps:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    haddps %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-SSE-NEXT:    haddps (%rdi), %xmm0 # sched: [8:1.00]
+; BTVER2-SSE-NEXT:    haddps %xmm1, %xmm0 # sched: [4:1.00]
+; BTVER2-SSE-NEXT:    haddps (%rdi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_haddps:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vhaddps %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; BTVER2-NEXT:    vhaddps (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_haddps:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    haddps %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    haddps (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_hsubpd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
 ; BDVER2-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_hsubpd:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    hsubpd %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-SSE-NEXT:    hsubpd (%rdi), %xmm0 # sched: [8:1.00]
+; BTVER2-SSE-NEXT:    hsubpd %xmm1, %xmm0 # sched: [4:1.00]
+; BTVER2-SSE-NEXT:    hsubpd (%rdi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_hsubpd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vhsubpd %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; BTVER2-NEXT:    vhsubpd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_hsubpd:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    hsubpd %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    hsubpd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_hsubps:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
 ; BDVER2-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_hsubps:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    hsubps %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-SSE-NEXT:    hsubps (%rdi), %xmm0 # sched: [8:1.00]
+; BTVER2-SSE-NEXT:    hsubps %xmm1, %xmm0 # sched: [4:1.00]
+; BTVER2-SSE-NEXT:    hsubps (%rdi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_hsubps:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vhsubps %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
+; BTVER2-NEXT:    vhsubps (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_hsubps:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    hsubps %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    hsubps (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

test/CodeGen/X86/ssse3-schedule.ll

 ; BDVER2-LABEL: test_phaddd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phaddd:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phaddd %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phaddd (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phaddd %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phaddd (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phaddd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphaddd %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphaddd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddd:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phaddd %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phaddd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_phaddsw:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phaddsw:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phaddsw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phaddsw (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phaddsw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phaddsw (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phaddsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphaddsw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphaddsw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddsw:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phaddsw %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phaddsw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_phaddw:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phaddw:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phaddw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phaddw (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phaddw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phaddw (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phaddw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphaddw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphaddw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phaddw:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phaddw %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phaddw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_phsubd:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phsubd:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phsubd %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phsubd (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phsubd %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phsubd (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phsubd:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphsubd %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphsubd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubd:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phsubd %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phsubd (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_phsubsw:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phsubsw:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phsubsw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phsubsw (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phsubsw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phsubsw (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phsubsw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphsubsw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphsubsw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubsw:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phsubsw %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phsubsw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

 ; BDVER2-LABEL: test_phsubw:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [5:0.50]
 ; BDVER2-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_phsubw:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    phsubw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT:    phsubw (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT:    phsubw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT:    phsubw (%rdi), %xmm0 # sched: [7:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_phsubw:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vphsubw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT:    vphsubw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_phsubw:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    phsubw %xmm1, %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    phsubw (%rdi), %xmm0 # sched: [100:0.25]
 ; ZNVER1-SSE-NEXT:    retq # sched: [1:0.50]
 ;

test/tools/llvm-mca/X86/BtVer2/dot-product.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=300 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 vmulps   %xmm0, %xmm1, %xmm2
 vhaddps  %xmm2, %xmm2, %xmm3
 vhaddps  %xmm3, %xmm3, %xmm4
 
 # CHECK:      Iterations:        300
 # CHECK-NEXT: Instructions:      900
-# CHECK-NEXT: Total Cycles:      610
+# CHECK-NEXT: Total Cycles:      611
 # CHECK-NEXT: Total uOps:        900
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.48
-# CHECK-NEXT: IPC:               1.48
+# CHECK-NEXT: uOps Per Cycle:    1.47
+# CHECK-NEXT: IPC:               1.47
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      2     1.00                        vmulps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      3     1.00                        vhaddps %xmm2, %xmm2, %xmm3
-# CHECK-NEXT:  1      3     1.00                        vhaddps %xmm3, %xmm3, %xmm4
+# CHECK-NEXT:  1      4     1.00                        vhaddps %xmm2, %xmm2, %xmm3
+# CHECK-NEXT:  1      4     1.00                        vhaddps %xmm3, %xmm3, %xmm4
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0

 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -     vhaddps %xmm2, %xmm2, %xmm3
 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -     vhaddps %xmm3, %xmm3, %xmm4
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
 # CHECK:      [0,0]     DeeER.    .    .   vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,1]     D==eeeER  .    .   vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [0,2]     .D====eeeER    .   vhaddps  %xmm3, %xmm3, %xmm4
-# CHECK-NEXT: [1,0]     .DeeE-----R    .   vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,1]     . D=eeeE---R   .   vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [1,2]     . D====eeeER   .   vhaddps  %xmm3, %xmm3, %xmm4
-# CHECK-NEXT: [2,0]     .  DeeE-----R  .   vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [2,1]     .  D====eeeER  .   vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [2,2]     .   D======eeeER   vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: [0,1]     D==eeeeER .    .   vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [0,2]     .D=====eeeeER  .   vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: [1,0]     .DeeE-------R  .   vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,1]     . D=eeeeE----R .   vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [1,2]     . D=====eeeeER .   vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: [2,0]     .  DeeE-------R.   vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [2,1]     .  D==eeeeE---R.   vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [2,2]     .   D=====eeeeER   vhaddps  %xmm3, %xmm3, %xmm4
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     1.0    1.0    3.3       vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1.     3     3.3    0.7    1.0       vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: 2.     3     5.7    0.0    0.0       vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: 0.     3     1.0    1.0    4.7       vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.     3     2.7    0.0    2.3       vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: 2.     3     6.0    0.0    0.0       vhaddps  %xmm3, %xmm3, %xmm4

test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vshufps $0, %xmm0, %xmm1, %xmm1
 vhaddps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      11
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.18
-# CHECK-NEXT: IPC:               0.18
+# CHECK-NEXT: uOps Per Cycle:    0.17
+# CHECK-NEXT: IPC:               0.17
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        vshufps $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT:  1      8     1.00    *                   vhaddps (%rdi), %xmm1, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   vhaddps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .    .   vshufps $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT: [0,1]     DeeeeeeeeER   vhaddps (%rdi), %xmm1, %xmm2
+# CHECK:      [0,0]     DeER .    ..   vshufps  $0, %xmm0, %xmm1, %xmm1
+# CHECK-NEXT: [0,1]     DeeeeeeeeeER   vhaddps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vshufps  $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT: 1.     1     1.0    0.0    0.0       vhaddps  (%rdi), %xmm1, %xmm2

test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vshufps $0, %xmm0, %xmm1, %xmm1
 vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      13
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.17
+# CHECK-NEXT: uOps Per Cycle:    0.23
+# CHECK-NEXT: IPC:               0.15
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        vshufps $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT:  2      8     2.00    *                   vhaddps (%rdi), %ymm1, %ymm2
+# CHECK-NEXT:  2      9     2.00    *                   vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .    ..   vshufps  $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT: [0,1]     .DeeeeeeeeER   vhaddps  (%rdi), %ymm1, %ymm2
+# CHECK:      [0,0]     DeER .    . .   vshufps $0, %xmm0, %xmm1, %xmm1
+# CHECK-NEXT: [0,1]     .DeeeeeeeeeER   vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vshufps  $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       vhaddps  (%rdi), %ymm1, %ymm2

test/tools/llvm-mca/X86/BtVer2/instruction-info-view.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=true < %s | FileCheck %s --check-prefix=ENABLED
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefix=DISABLED
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info < %s | FileCheck %s -check-prefix=ENABLED
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false < %s | FileCheck %s -check-prefix=ENABLED
 
 vmulps   %xmm0, %xmm1, %xmm2
 vhaddps  %xmm2, %xmm2, %xmm3
 vhaddps  %xmm3, %xmm3, %xmm4
 
 # DISABLED-NOT: Instruction Info:
 
 
 # ENABLED:       Iterations:        100
 # ENABLED-NEXT:  Instructions:      300
-# ENABLED-NEXT:  Total Cycles:      209
+# ENABLED-NEXT:  Total Cycles:      211
 # ENABLED-NEXT:  Total uOps:        300
 
 
 # ENABLED:       Dispatch Width:    2
-# ENABLED-NEXT:  uOps Per Cycle:    1.44
-# ENABLED-NEXT:  IPC:               1.44
+# ENABLED-NEXT:  uOps Per Cycle:    1.42
+# ENABLED-NEXT:  IPC:               1.42
 # ENABLED-NEXT:  Block RThroughput: 2.0
 
 # ENABLED:       Instruction Info:
 # ENABLED-NEXT:  [1]: #uOps
 # ENABLED-NEXT:  [2]: Latency
 # ENABLED-NEXT:  [3]: RThroughput
 # ENABLED-NEXT:  [4]: MayLoad
 # ENABLED-NEXT:  [5]: MayStore
 # ENABLED-NEXT:  [6]: HasSideEffects (U)
 
 # ENABLED:       [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # ENABLED-NEXT:   1      2     1.00                        vmulps %xmm0, %xmm1, %xmm2
-# ENABLED-NEXT:   1      3     1.00                        vhaddps  %xmm2, %xmm2, %xmm3
-# ENABLED-NEXT:   1      3     1.00                        vhaddps  %xmm3, %xmm3, %xmm4
+# ENABLED-NEXT:   1      4     1.00                        vhaddps  %xmm2, %xmm2, %xmm3
+# ENABLED-NEXT:   1      4     1.00                        vhaddps  %xmm3, %xmm3, %xmm4

test/tools/llvm-mca/X86/BtVer2/resources-avx1.s

 # CHECK-NEXT:  5      11    3.00                        vdpps $22, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  5      16    3.00    *                   vdpps $22, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  10     12    6.00                        vdpps $22, %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  10     17    6.00    *                   vdpps $22, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vextractf128  $1, %ymm0, %xmm2
 # CHECK-NEXT:  1      1     1.00           *            vextractf128  $1, %ymm0, (%rax)
 # CHECK-NEXT:  1      3     1.00                        vextractps  $1, %xmm0, %ecx
 # CHECK-NEXT:  1      3     1.00           *            vextractps  $1, %xmm0, (%rax)
-# CHECK-NEXT:  1      3     1.00                        vhaddpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   vhaddpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      3     2.00                        vhaddpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  2      8     2.00    *                   vhaddpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      3     1.00                        vhaddps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   vhaddps (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      3     2.00                        vhaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  2      8     2.00    *                   vhaddps (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      3     1.00                        vhsubpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   vhsubpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      3     2.00                        vhsubpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  2      8     2.00    *                   vhsubpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT:  1      3     1.00                        vhsubps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   vhsubps (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      3     2.00                        vhsubps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT:  2      8     2.00    *                   vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      4     1.00                        vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  2      4     2.00                        vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  2      9     2.00    *                   vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      4     1.00                        vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  2      4     2.00                        vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  2      9     2.00    *                   vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      4     1.00                        vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  2      4     2.00                        vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  2      9     2.00    *                   vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT:  1      4     1.00                        vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  2      4     2.00                        vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  2      9     2.00    *                   vhsubps (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  2      1     1.00                        vinsertf128 $1, %xmm0, %ymm1, %ymm2
 # CHECK-NEXT:  2      6     1.00    *                   vinsertf128 $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  1      1     0.50                        vinsertps $1, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   vinsertps $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00    *                   vlddqu  (%rax), %xmm2
 # CHECK-NEXT:  1      5     1.00    *                   vlddqu  (%rax), %ymm2
 # CHECK-NEXT:  1      5     1.00    *      *      U     vldmxcsr  (%rax)
 # CHECK-NEXT:  1      1     1.00    *      *      U     vmaskmovdqu %xmm0, %xmm1

 # CHECK-NEXT:  1      3     1.00                        vpextrb $1, %xmm0, %ecx
 # CHECK-NEXT:  1      3     1.00           *            vpextrb $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      3     1.00                        vpextrd $1, %xmm0, %ecx
 # CHECK-NEXT:  1      3     1.00           *            vpextrd $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      3     1.00                        vpextrq $1, %xmm0, %rcx
 # CHECK-NEXT:  1      3     1.00           *            vpextrq $1, %xmm0, (%rax)
 # CHECK-NEXT:  1      3     1.00                        vpextrw $1, %xmm0, %ecx
 # CHECK-NEXT:  1      3     1.00           *            vpextrw $1, %xmm0, (%rax)
-# CHECK-NEXT:  1      1     0.50                        vphaddd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphaddd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     0.50                        vphaddsw  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphaddsw  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     0.50                        vphaddw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphaddsw  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphaddsw  (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphaddw (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      2     0.50                        vphminposuw %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   vphminposuw (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        vphsubd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphsubd (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     0.50                        vphsubsw  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphsubsw  (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  1      1     0.50                        vphsubw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphsubsw  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphsubsw  (%rax), %xmm1, %xmm2
+# CHECK-NEXT:  1      2     0.50                        vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   vphsubw (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      7     0.50                        vpinsrb $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00    *                   vpinsrb $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      7     0.50                        vpinsrd $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00    *                   vpinsrd $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      7     0.50                        vpinsrq $1, %rax, %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00    *                   vpinsrq $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      7     0.50                        vpinsrw $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00    *                   vpinsrw $1, (%rax), %xmm1, %xmm2

test/tools/llvm-mca/X86/BtVer2/resources-sse3.s

 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                        addsubpd  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   addsubpd  (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        addsubps  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   addsubps  (%rax), %xmm2
-# CHECK-NEXT:  1      3     1.00                        haddpd  %xmm0, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   haddpd  (%rax), %xmm2
-# CHECK-NEXT:  1      3     1.00                        haddps  %xmm0, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   haddps  (%rax), %xmm2
-# CHECK-NEXT:  1      3     1.00                        hsubpd  %xmm0, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   hsubpd  (%rax), %xmm2
-# CHECK-NEXT:  1      3     1.00                        hsubps  %xmm0, %xmm2
-# CHECK-NEXT:  1      8     1.00    *                   hsubps  (%rax), %xmm2
+# CHECK-NEXT:  1      4     1.00                        haddpd  %xmm0, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   haddpd  (%rax), %xmm2
+# CHECK-NEXT:  1      4     1.00                        haddps  %xmm0, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   haddps  (%rax), %xmm2
+# CHECK-NEXT:  1      4     1.00                        hsubpd  %xmm0, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   hsubpd  (%rax), %xmm2
+# CHECK-NEXT:  1      4     1.00                        hsubps  %xmm0, %xmm2
+# CHECK-NEXT:  1      9     1.00    *                   hsubps  (%rax), %xmm2
 # CHECK-NEXT:  1      5     1.00    *                   lddqu (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        movddup %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   movddup (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        movshdup  %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   movshdup  (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        movsldup  %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   movsldup  (%rax), %xmm2
 

test/tools/llvm-mca/X86/BtVer2/resources-ssse3.s

 # CHECK-NEXT:  1      1     0.50                        pabsw %mm0, %mm2
 # CHECK-NEXT:  1      6     1.00    *                   pabsw (%rax), %mm2
 # CHECK-NEXT:  1      1     0.50                        pabsw %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   pabsw (%rax), %xmm2
 # CHECK-NEXT:  1      1     0.50                        palignr $1, %mm0, %mm2
 # CHECK-NEXT:  1      6     1.00    *                   palignr $1, (%rax), %mm2
 # CHECK-NEXT:  1      1     0.50                        palignr $1, %xmm0, %xmm2
 # CHECK-NEXT:  1      6     1.00    *                   palignr $1, (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phaddd  %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddd  (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phaddd  %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddd  (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phaddsw %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddsw (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phaddsw %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddsw (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phaddw  %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddw  (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phaddw  %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phaddw  (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phsubd  %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubd  (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phsubd  %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubd  (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phsubsw %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubsw (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phsubsw %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubsw (%rax), %xmm2
-# CHECK-NEXT:  1      1     0.50                        phsubw  %mm0, %mm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubw  (%rax), %mm2
-# CHECK-NEXT:  1      1     0.50                        phsubw  %xmm0, %xmm2
-# CHECK-NEXT:  1      6     1.00    *                   phsubw  (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phaddd  %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddd  (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phaddd  %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddd  (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phaddsw %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddsw (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phaddsw %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddsw (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phaddw  %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddw  (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phaddw  %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phaddw  (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phsubd  %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubd  (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phsubd  %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubd  (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phsubsw %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubsw (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phsubsw %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubsw (%rax), %xmm2
+# CHECK-NEXT:  1      2     0.50                        phsubw  %mm0, %mm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubw  (%rax), %mm2
+# CHECK-NEXT:  1      2     0.50                        phsubw  %xmm0, %xmm2
+# CHECK-NEXT:  1      7     1.00    *                   phsubw  (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        pmaddubsw %mm0, %mm2
 # CHECK-NEXT:  1      7     1.00    *                   pmaddubsw (%rax), %mm2
 # CHECK-NEXT:  1      2     1.00                        pmaddubsw %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   pmaddubsw (%rax), %xmm2
 # CHECK-NEXT:  1      2     1.00                        pmulhrsw  %mm0, %mm2
 # CHECK-NEXT:  1      7     1.00    *                   pmulhrsw  (%rax), %mm2
 # CHECK-NEXT:  1      2     1.00                        pmulhrsw  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   pmulhrsw  (%rax), %xmm2