This is an archive of the discontinued LLVM Phabricator instance.

[X86] Use X86ISD::BLENDV for blendv intrinsics. Replace vselect with blendv just before isel table lookup. Remove vselect isel patterns.
ClosedPublic

Authored by craig.topper on Jan 15 2019, 11:54 PM.

Details

Summary

This cleans up the duplication we have with both intrinsic isel patterns and vselect isel patterns. This should also allow the intrinsics to demanded bits support for the condition.

I've switched the canonical pattern in isel to use the X86ISD::BLENDV node instead of VSELECT. Since it always seemed weird to move from BLENDV with its relaxed rules on condition bits to VSELECT which has strict rules about all bits of the condition element being the same. Its more correct to go from VSELECT to BLENDV.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 15 2019, 11:54 PM
RKSimon added inline comments.Jan 16 2019, 2:03 AM
lib/Target/X86/X86ISelDAGToDAG.cpp
3385

worth asserting that SSE41 is present?

Add assert for SSE4.1

RKSimon accepted this revision.Jan 16 2019, 1:26 PM

LGTM

lib/Target/X86/X86ISelLowering.cpp
21783

Can you use VT here?

This revision is now accepted and ready to land.Jan 16 2019, 1:26 PM
This revision was automatically updated to reflect the committed changes.