This is an archive of the discontinued LLVM Phabricator instance.

Differential D55935

[X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
ClosedPublic

Authored by RKSimon on Dec 20 2018, 8:23 AM.

Details

Reviewers
spatel
craig.topper
lebedev.ri
Commits
rG933673d8786a: [X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
rL351819: [X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
Summary

For constant bit select patterns, replace one AND with a ANDNP, allowing us to reuse the constant mask. This prevents some load-folding but removes a constant pool vector entry, which I think is the right trade off.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Dec 20 2018, 8:23 AM
craig.topper added inline comments.Dec 20 2018, 1:07 PM
lib/Target/X86/X86ISelLowering.cpp
36273 ↗(On Diff #179084)

What about 512bit?

craig.topper added inline comments.Dec 20 2018, 1:18 PM
lib/Target/X86/X86ISelLowering.cpp
36273 ↗(On Diff #179084)

We're after type legalization here. Can this just check isVector?

RKSimon updated this revision to Diff 179256.Dec 21 2018, 2:37 AM

Accept all (legal) vector types to canonicalizeBitSelect

RKSimon updated this revision to Diff 179270.Dec 21 2018, 5:15 AM

Fixed combine-fcopysign.ll regressions by adding X86ISD::FOR computeKnownBits support

spatel added a comment.Dec 23 2018, 10:20 AM

Would we better off doing a generic DAGCombine into the optimal xor-and-xor (aka, masked merge) pattern?
(x & C) | (y & ~C) --> ((x ^ y) & C) ^ y

That should allow load folding of the constant, so it never burns a register to hold the constant.

We weren't allowed to do that transform with a variable mask in D46814 because:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20180528/556578.html

But I think that's ok with a constant mask. We can't accidentally dynamically access an undef value when the mask is a constant.

lebedev.ri added a comment.Dec 24 2018, 3:09 AM
In D55935#1340459, @spatel wrote:

Would we better off doing a generic DAGCombine into the optimal xor-and-xor (aka, masked merge) pattern?
(x & C) | (y & ~C) --> ((x ^ y) & C) ^ y

We weren't allowed to do that transform with a variable mask in D46814 because:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20180528/556578.html

But I think that's ok with a constant mask. We can't accidentally dynamically access an undef value when the mask is a constant.

To add to that, i *think* we intentionally avoided transforming the pattern with constants there, IIRC because that was better for ValueTracking?

That should allow load folding of the constant, so it never burns a register to hold the constant.

I think that would work.
But there will likely be some cost to that: https://godbolt.org/z/-MZNgY

RKSimon edited the summary of this revision. (Show Details)Jan 7 2019, 8:05 AM
RKSimon added a comment.Jan 7 2019, 8:13 AM
In D55935#1340459, @spatel wrote:

Would we better off doing a generic DAGCombine into the optimal xor-and-xor (aka, masked merge) pattern?
(x & C) | (y & ~C) --> ((x ^ y) & C) ^ y --> ((y ^ x) & ~C) ^ x

So do we agree that adding support for this additional pattern only makes sense if one of X or Y is being loaded (once)? It doesn't seem to matter if C is being reused or not.

spatel added a comment.Jan 7 2019, 9:05 AM
In D55935#1348305, @RKSimon wrote:
In D55935#1340459, @spatel wrote:

Would we better off doing a generic DAGCombine into the optimal xor-and-xor (aka, masked merge) pattern?
(x & C) | (y & ~C) --> ((x ^ y) & C) ^ y --> ((y ^ x) & ~C) ^ x

So do we agree that adding support for this additional pattern only makes sense if one of X or Y is being loaded (once)? It doesn't seem to matter if C is being reused or not.

I'm not seeing where loading X/Y is the deciding factor. We have something like this currently:

andps {{.*}}(%rip), %xmm1  // load constant
andps {{.*}}(%rip), %xmm2  // load inverse constant
orps  %xmm2, %xmm1

This would become with this patch:

movaps  {{.*}}(%rip), %xmm0 // load constant for 2 uses
andps   %xmm0, %xmm1
andnps  %xmm0, %xmm2
orps    %xmm2, %xmm1

With the masked-merge transform it would be:

xorps  %xmm1, %xmm2
andps  {{.*}}(%rip), %xmm2 // load fold constant for 1 use
xorps  %xmm2, %xmm1

It's 4 uops for either of the last 2 alternatives. The trade-off (which I think is impossible to model statically) is whether we're better off with the potentially better thoughput of the sequence with 'andnps' or the potentially shorter (load-folded) sequence with the dependent logic ops. Either way is a uop improvement over the current codegen, so I'm not opposed to this patch, but the generic masked-merge transform would probably be a smaller patch?

RKSimon added a comment.Jan 7 2019, 9:43 AM

Exactly - which is why I said only the cases where X and/or Y are loaded: https://godbolt.org/z/2qMqiF has examples where this would reduce loads and improve folding opportunities.

But getting the XOR variant emitted will be painful as DAGCombiner::unfoldMaskedMerge is fighting against us all the way.

RKSimon updated this revision to Diff 180514.Jan 7 2019, 9:55 AM

rebase

RKSimon mentioned this in rL350548: [X86] Add OR(AND(X,C),AND(Y,~C)) bit select tests.Jan 7 2019, 10:13 AM
RKSimon updated this revision to Diff 180519.Jan 7 2019, 10:23 AM

rebase

RKSimon planned changes to this revision.Jan 7 2019, 10:28 AM

I'm going to refactor this so it only kicks in on XOP or when any of the masks have multiple uses.

RKSimon updated this revision to Diff 181775.Jan 15 2019, 6:28 AM

Only canonicalize the pattern if the target is XOP (which will use the PCMOV instruction) or the mask has multiple uses.

RKSimon added a comment.Jan 21 2019, 2:17 PM

ping?

lebedev.ri added a comment.Jan 21 2019, 2:45 PM

Looks good to me, no further comments.

lib/Target/X86/X86ISelLowering.cpp
30146–30166 ↗(On Diff #181775)

I guess this is can go separately.

spatel accepted this revision.Jan 21 2019, 3:17 PM

LGTM

This revision is now accepted and ready to land.Jan 21 2019, 3:17 PM
Closed by commit rL351819: [X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y)) (authored by RKSimon). · Explain WhyJan 22 2019, 5:47 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 182897

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 30,227 Lines • ▼ Show 20 Lines if (!!DemandedRHS) {
Known.Zero &= Known2.Zero; Known.Zero &= Known2.Zero;
} }
if (Known.countMinLeadingZeros() < BitWidth) if (Known.countMinLeadingZeros() < BitWidth)
Known.resetAll(); Known.resetAll();
Known = Known.trunc(BitWidth); Known = Known.trunc(BitWidth);
break; break;
} }
case X86ISD::ANDNP: {
KnownBits Known2;
Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Known2 = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
// ANDNP = (~X & Y);
Known.One &= Known2.Zero;
Known.Zero |= Known2.One;
break;
}
case X86ISD::FOR: {
KnownBits Known2;
Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Known2 = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
// Output known-0 bits are only known if clear in both the LHS & RHS.
Known.Zero &= Known2.Zero;
// Output known-1 are known to be set if set in either the LHS | RHS.
Known.One |= Known2.One;
break;
}
case X86ISD::CMOV: { case X86ISD::CMOV: {
Known = DAG.computeKnownBits(Op.getOperand(1), Depth+1); Known = DAG.computeKnownBits(Op.getOperand(1), Depth+1);
// If we don't know any bits, early out. // If we don't know any bits, early out.
if (Known.isUnknown()) if (Known.isUnknown())
break; break;
KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth+1); KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth+1);
// Only known if known in both the LHS and RHS. // Only known if known in both the LHS and RHS.
▲ Show 20 Lines • Show All 6,270 Lines • ▼ Show 20 Lines if (VT == SrcVecVT.getScalarType() &&
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), VT, Shuffle, return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), VT, Shuffle,
N->getOperand(0).getOperand(1)); N->getOperand(0).getOperand(1));
} }
} }
return SDValue(); return SDValue();
} }
// Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
static SDValue canonicalizeBitSelect(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
EVT VT = N->getValueType(0);
if (!VT.isVector())
return SDValue();
SDValue N0 = peekThroughBitcasts(N->getOperand(0));
SDValue N1 = peekThroughBitcasts(N->getOperand(1));
if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
return SDValue();
// On XOP we'll lower to PCMOV so accept one use, otherwise only
// do this if either mask has multiple uses already.
if (!(Subtarget.hasXOP() || !N0.getOperand(1).hasOneUse() ||
!N1.getOperand(1).hasOneUse()))
return SDValue();
// Attempt to extract constant byte masks.
APInt UndefElts0, UndefElts1;
SmallVector<APInt, 32> EltBits0, EltBits1;
if (!getTargetConstantBitsFromNode(N0.getOperand(1), 8, UndefElts0, EltBits0,
false, false))
return SDValue();
if (!getTargetConstantBitsFromNode(N1.getOperand(1), 8, UndefElts1, EltBits1,
false, false))
return SDValue();
for (unsigned i = 0, e = EltBits0.size(); i != e; ++i) {
// TODO - add UNDEF elts support.
if (UndefElts0[i] || UndefElts1[i])
return SDValue();
if (EltBits0[i] != ~EltBits1[i])
return SDValue();
}
SDLoc DL(N);
SDValue X = N->getOperand(0);
SDValue Y =
DAG.getNode(X86ISD::ANDNP, DL, VT, DAG.getBitcast(VT, N0.getOperand(1)),
DAG.getBitcast(VT, N1.getOperand(0)));
return DAG.getNode(ISD::OR, DL, VT, X, Y);
}
// Try to match OR(AND(~MASK,X),AND(MASK,Y)) logic pattern. // Try to match OR(AND(~MASK,X),AND(MASK,Y)) logic pattern.
static bool matchLogicBlend(SDNode *N, SDValue &X, SDValue &Y, SDValue &Mask) { static bool matchLogicBlend(SDNode *N, SDValue &X, SDValue &Y, SDValue &Mask) {
if (N->getOpcode() != ISD::OR) if (N->getOpcode() != ISD::OR)
return false; return false;
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1); SDValue N1 = N->getOperand(1);
▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines if (DCI.isBeforeLegalizeOps())
return SDValue(); return SDValue();
if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget)) if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
return R; return R;
if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget)) if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
return FPLogic; return FPLogic;
if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
return R;
if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget)) if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
return R; return R;
// Attempt to recursively combine an OR of shuffles. // Attempt to recursively combine an OR of shuffles.
if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) { if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
SDValue Op(N, 0); SDValue Op(N, 0);
if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget)) if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
return Res; return Res;
▲ Show 20 Lines • Show All 6,012 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitreverse.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X64-NEXT: movdqa %xmm0, %xmm2 ; X64-NEXT: movdqa %xmm0, %xmm2
; X64-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X64-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; X64-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; X64-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; X64-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; X64-NEXT: pshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,7,6,5,4]
; X64-NEXT: packuswb %xmm2, %xmm0 ; X64-NEXT: packuswb %xmm2, %xmm1
; X64-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X64-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X64-NEXT: movdqa %xmm0, %xmm2 ; X64-NEXT: movdqa %xmm1, %xmm2
; X64-NEXT: pand %xmm1, %xmm2 ; X64-NEXT: pand %xmm0, %xmm2
; X64-NEXT: psllw $4, %xmm2 ; X64-NEXT: psllw $4, %xmm2
; X64-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; X64-NEXT: pand {{.*}}(%rip), %xmm1
; X64-NEXT: pand %xmm3, %xmm2 ; X64-NEXT: psrlw $4, %xmm1
; X64-NEXT: pand %xmm3, %xmm0 ; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: psrlw $4, %xmm0 ; X64-NEXT: pandn %xmm2, %xmm0
; X64-NEXT: pand %xmm1, %xmm0 ; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: por %xmm2, %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; X64-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X64-NEXT: pand %xmm0, %xmm1 ; X64-NEXT: pand %xmm0, %xmm1
; X64-NEXT: psllw $2, %xmm1 ; X64-NEXT: psllw $2, %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm1 ; X64-NEXT: pand {{.*}}(%rip), %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: psrlw $2, %xmm0 ; X64-NEXT: psrlw $2, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: por %xmm1, %xmm0 ; X64-NEXT: por %xmm1, %xmm0
▲ Show 20 Lines • Show All 1,060 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/combine-bitselect.ll

Show All 13 Lines
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: orps %xmm1, %xmm0 ; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v2i64_rr: ; XOP-LABEL: bitselect_v2i64_rr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vorps %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v2i64_rr: ; AVX-LABEL: bitselect_v2i64_rr:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
Show All 9 Lines
; SSE-NEXT: movaps (%rdi), %xmm1 ; SSE-NEXT: movaps (%rdi), %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: orps %xmm1, %xmm0 ; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v2i64_rm: ; XOP-LABEL: bitselect_v2i64_rm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %xmm1 ; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vorps %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v2i64_rm: ; AVX-LABEL: bitselect_v2i64_rm:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm1 ; AVX-NEXT: vmovaps (%rdi), %xmm1
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
Show All 11 Lines
; SSE-NEXT: movaps (%rdi), %xmm1 ; SSE-NEXT: movaps (%rdi), %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0 ; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v2i64_mr: ; XOP-LABEL: bitselect_v2i64_mr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %xmm1 ; XOP-NEXT: vmovdqa (%rdi), %xmm1
; XOP-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; XOP-NEXT: vpcmov {{.*}}(%rip), %xmm0, %xmm1, %xmm0
; XOP-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vorps %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v2i64_mr: ; AVX-LABEL: bitselect_v2i64_mr:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm1 ; AVX-NEXT: vmovaps (%rdi), %xmm1
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
Show All 12 Lines
; SSE-NEXT: movaps (%rsi), %xmm0 ; SSE-NEXT: movaps (%rsi), %xmm0
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: orps %xmm1, %xmm0 ; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v2i64_mm: ; XOP-LABEL: bitselect_v2i64_mm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %xmm0 ; XOP-NEXT: vmovdqa (%rsi), %xmm0
; XOP-NEXT: vmovaps (%rsi), %xmm1 ; XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551612,18446744065119617022]
; XOP-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpcmov %xmm1, (%rdi), %xmm0, %xmm0
; XOP-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vorps %xmm0, %xmm1, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v2i64_mm: ; AVX-LABEL: bitselect_v2i64_mm:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm0 ; AVX-NEXT: vmovaps (%rdi), %xmm0
; AVX-NEXT: vmovaps (%rsi), %xmm1 ; AVX-NEXT: vmovaps (%rsi), %xmm1
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
Show All 19 Lines
; SSE-NEXT: andps {{.*}}(%rip), %xmm3 ; SSE-NEXT: andps {{.*}}(%rip), %xmm3
; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm3, %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm2 ; SSE-NEXT: andps {{.*}}(%rip), %xmm2
; SSE-NEXT: orps %xmm2, %xmm0 ; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v4i64_rr: ; XOP-LABEL: bitselect_v4i64_rr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; XOP-NEXT: vorps %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v4i64_rr: ; AVX-LABEL: bitselect_v4i64_rr:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0 ; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%3 = and <4 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890> %3 = and <4 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <4 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891> %4 = and <4 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
%5 = or <4 x i64> %4, %3 %5 = or <4 x i64> %4, %3
ret <4 x i64> %5 ret <4 x i64> %5
} }
define <4 x i64> @bitselect_v4i64_rm(<4 x i64>, <4 x i64>* nocapture readonly) { define <4 x i64> @bitselect_v4i64_rm(<4 x i64>, <4 x i64>* nocapture readonly) {
; SSE-LABEL: bitselect_v4i64_rm: ; SSE-LABEL: bitselect_v4i64_rm:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [8589934593,3]
; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: andps %xmm2, %xmm0
; SSE-NEXT: movaps {{.*#+}} xmm2 = [18446744065119617022,18446744073709551612] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [18446744065119617022,18446744073709551612]
; SSE-NEXT: movaps 16(%rdi), %xmm3 ; SSE-NEXT: movaps 16(%rdi), %xmm4
; SSE-NEXT: andps %xmm2, %xmm3 ; SSE-NEXT: andps %xmm2, %xmm4
; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: movaps (%rdi), %xmm5
; SSE-NEXT: andps (%rdi), %xmm2 ; SSE-NEXT: andps %xmm2, %xmm5
; SSE-NEXT: orps %xmm2, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andnps %xmm0, %xmm3
; SSE-NEXT: orps %xmm5, %xmm3
; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm4, %xmm2
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: movaps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v4i64_rm: ; XOP-LABEL: bitselect_v4i64_rm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %ymm1 ; XOP-NEXT: vmovdqa (%rdi), %ymm1
; XOP-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; XOP-NEXT: vorps %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v4i64_rm: ; AVX-LABEL: bitselect_v4i64_rm:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm1 ; AVX-NEXT: vmovaps (%rdi), %ymm1
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0 ; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %1 %3 = load <4 x i64>, <4 x i64>* %1
%4 = and <4 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3> %4 = and <4 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3>
%5 = and <4 x i64> %3, <i64 -8589934594, i64 -4, i64 -8589934594, i64 -4> %5 = and <4 x i64> %3, <i64 -8589934594, i64 -4, i64 -8589934594, i64 -4>
%6 = or <4 x i64> %5, %4 %6 = or <4 x i64> %5, %4
ret <4 x i64> %6 ret <4 x i64> %6
} }
define <4 x i64> @bitselect_v4i64_mr(<4 x i64>* nocapture readonly, <4 x i64>) { define <4 x i64> @bitselect_v4i64_mr(<4 x i64>* nocapture readonly, <4 x i64>) {
; SSE-LABEL: bitselect_v4i64_mr: ; SSE-LABEL: bitselect_v4i64_mr:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [12884901890,4294967296] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [12884901890,4294967296]
; SSE-NEXT: movaps 16(%rdi), %xmm3 ; SSE-NEXT: movaps 16(%rdi), %xmm4
; SSE-NEXT: andps %xmm2, %xmm3 ; SSE-NEXT: andps %xmm2, %xmm4
; SSE-NEXT: andps (%rdi), %xmm2 ; SSE-NEXT: movaps (%rdi), %xmm5
; SSE-NEXT: movaps {{.*#+}} xmm4 = [18446744060824649725,18446744069414584319] ; SSE-NEXT: andps %xmm2, %xmm5
; SSE-NEXT: andps %xmm4, %xmm1 ; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: andnps %xmm0, %xmm3
; SSE-NEXT: andps %xmm4, %xmm0 ; SSE-NEXT: orps %xmm5, %xmm3
; SSE-NEXT: orps %xmm2, %xmm0 ; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm4, %xmm2
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: movaps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v4i64_mr: ; XOP-LABEL: bitselect_v4i64_mr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %ymm1 ; XOP-NEXT: vmovdqa (%rdi), %ymm1
; XOP-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1 ; XOP-NEXT: vpcmov {{.*}}(%rip), %ymm0, %ymm1, %ymm0
; XOP-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; XOP-NEXT: vorps %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v4i64_mr: ; AVX-LABEL: bitselect_v4i64_mr:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm1 ; AVX-NEXT: vmovaps (%rdi), %ymm1
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0 ; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %0 %3 = load <4 x i64>, <4 x i64>* %0
%4 = and <4 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296> %4 = and <4 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296>
%5 = and <4 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297> %5 = and <4 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297>
%6 = or <4 x i64> %4, %5 %6 = or <4 x i64> %4, %5
ret <4 x i64> %6 ret <4 x i64> %6
} }
define <4 x i64> @bitselect_v4i64_mm(<4 x i64>* nocapture readonly, <4 x i64>* nocapture readonly) { define <4 x i64> @bitselect_v4i64_mm(<4 x i64>* nocapture readonly, <4 x i64>* nocapture readonly) {
; SSE-LABEL: bitselect_v4i64_mm: ; SSE-LABEL: bitselect_v4i64_mm:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm2 = [3,8589934593] ; SSE-NEXT: movaps {{.*#+}} xmm1 = [18446744073709551612,18446744065119617022]
; SSE-NEXT: movaps 16(%rdi), %xmm3 ; SSE-NEXT: movaps 16(%rsi), %xmm2
; SSE-NEXT: andps %xmm2, %xmm3 ; SSE-NEXT: andps %xmm1, %xmm2
; SSE-NEXT: andps (%rdi), %xmm2 ; SSE-NEXT: movaps (%rsi), %xmm3
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551612,18446744065119617022] ; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: movaps 16(%rsi), %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: andps %xmm0, %xmm1 ; SSE-NEXT: andnps (%rdi), %xmm0
; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm3, %xmm0
; SSE-NEXT: andps (%rsi), %xmm0 ; SSE-NEXT: andnps 16(%rdi), %xmm1
; SSE-NEXT: orps %xmm2, %xmm0 ; SSE-NEXT: orps %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v4i64_mm: ; XOP-LABEL: bitselect_v4i64_mm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps (%rdi), %ymm0 ; XOP-NEXT: vmovdqa (%rsi), %ymm0
; XOP-NEXT: vmovaps (%rsi), %ymm1 ; XOP-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
; XOP-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; XOP-NEXT: vpcmov %ymm1, (%rdi), %ymm0, %ymm0
; XOP-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; XOP-NEXT: vorps %ymm0, %ymm1, %ymm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX-LABEL: bitselect_v4i64_mm: ; AVX-LABEL: bitselect_v4i64_mm:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %ymm0 ; AVX-NEXT: vmovaps (%rdi), %ymm0
; AVX-NEXT: vmovaps (%rsi), %ymm1 ; AVX-NEXT: vmovaps (%rsi), %ymm1
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
Show All 9 Lines
; ;
; 512-bit vectors ; 512-bit vectors
; ;
define <8 x i64> @bitselect_v8i64_rr(<8 x i64>, <8 x i64>) { define <8 x i64> @bitselect_v8i64_rr(<8 x i64>, <8 x i64>) {
; SSE-LABEL: bitselect_v8i64_rr: ; SSE-LABEL: bitselect_v8i64_rr:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm8 = [12884901890,12884901890]
; SSE-NEXT: andps %xmm8, %xmm3
; SSE-NEXT: movaps {{.*#+}} xmm9 = [4294967296,12884901890]
; SSE-NEXT: andps %xmm9, %xmm2
; SSE-NEXT: andps %xmm8, %xmm1
; SSE-NEXT: andps %xmm9, %xmm0
; SSE-NEXT: movaps {{.*#+}} xmm8 = [18446744060824649725,18446744060824649725] ; SSE-NEXT: movaps {{.*#+}} xmm8 = [18446744060824649725,18446744060824649725]
; SSE-NEXT: andps %xmm8, %xmm7 ; SSE-NEXT: andps %xmm8, %xmm7
; SSE-NEXT: orps %xmm7, %xmm3 ; SSE-NEXT: movaps {{.*#+}} xmm9 = [18446744069414584319,18446744060824649725]
; SSE-NEXT: movaps {{.*#+}} xmm7 = [18446744069414584319,18446744060824649725] ; SSE-NEXT: andps %xmm9, %xmm6
; SSE-NEXT: andps %xmm7, %xmm6 ; SSE-NEXT: andps %xmm8, %xmm5
; SSE-NEXT: orps %xmm6, %xmm2 ; SSE-NEXT: andps %xmm9, %xmm4
; SSE-NEXT: andps %xmm5, %xmm8 ; SSE-NEXT: movaps %xmm9, %xmm10
; SSE-NEXT: orps %xmm8, %xmm1 ; SSE-NEXT: andnps %xmm0, %xmm10
; SSE-NEXT: andps %xmm4, %xmm7 ; SSE-NEXT: orps %xmm4, %xmm10
; SSE-NEXT: orps %xmm7, %xmm0 ; SSE-NEXT: movaps %xmm8, %xmm4
; SSE-NEXT: andnps %xmm1, %xmm4
; SSE-NEXT: orps %xmm5, %xmm4
; SSE-NEXT: andnps %xmm2, %xmm9
; SSE-NEXT: orps %xmm6, %xmm9
; SSE-NEXT: andnps %xmm3, %xmm8
; SSE-NEXT: orps %xmm7, %xmm8
; SSE-NEXT: movaps %xmm10, %xmm0
; SSE-NEXT: movaps %xmm4, %xmm1
; SSE-NEXT: movaps %xmm9, %xmm2
; SSE-NEXT: movaps %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v8i64_rr: ; XOP-LABEL: bitselect_v8i64_rr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovaps {{.*#+}} ymm4 = [4294967296,12884901890,12884901890,12884901890] ; XOP-NEXT: vmovdqa {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
; XOP-NEXT: vandps %ymm4, %ymm1, %ymm1 ; XOP-NEXT: vpcmov %ymm4, %ymm0, %ymm2, %ymm0
; XOP-NEXT: vandps %ymm4, %ymm0, %ymm0 ; XOP-NEXT: vpcmov %ymm4, %ymm1, %ymm3, %ymm1
; XOP-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
; XOP-NEXT: vandps %ymm4, %ymm3, %ymm3
; XOP-NEXT: vorps %ymm1, %ymm3, %ymm1
; XOP-NEXT: vandps %ymm4, %ymm2, %ymm2
; XOP-NEXT: vorps %ymm0, %ymm2, %ymm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; AVX1-LABEL: bitselect_v8i64_rr: ; AVX1-LABEL: bitselect_v8i64_rr:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovaps {{.*#+}} ymm4 = [4294967296,12884901890,12884901890,12884901890]
; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1
; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725] ; AVX1-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
; AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3 ; AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3
; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2 ; AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2
; AVX1-NEXT: vandnps %ymm0, %ymm4, %ymm0
; AVX1-NEXT: vorps %ymm0, %ymm2, %ymm0 ; AVX1-NEXT: vorps %ymm0, %ymm2, %ymm0
; AVX1-NEXT: vandnps %ymm1, %ymm4, %ymm1
; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: bitselect_v8i64_rr: ; AVX2-LABEL: bitselect_v8i64_rr:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps {{.*#+}} ymm4 = [4294967296,12884901890,12884901890,12884901890]
; AVX2-NEXT: vandps %ymm4, %ymm1, %ymm1
; AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725] ; AVX2-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
; AVX2-NEXT: vandps %ymm4, %ymm3, %ymm3 ; AVX2-NEXT: vandps %ymm4, %ymm3, %ymm3
; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vandps %ymm4, %ymm2, %ymm2 ; AVX2-NEXT: vandps %ymm4, %ymm2, %ymm2
; AVX2-NEXT: vandnps %ymm0, %ymm4, %ymm0
; AVX2-NEXT: vorps %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vorps %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vandnps %ymm1, %ymm4, %ymm1
; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: bitselect_v8i64_rr: ; AVX512F-LABEL: bitselect_v8i64_rr:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0 ; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512F-NEXT: vporq %zmm0, %zmm1, %zmm0 ; AVX512F-NEXT: vporq %zmm0, %zmm1, %zmm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
%3 = and <8 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890, i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890> %3 = and <8 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890, i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <8 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891> %4 = and <8 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
%5 = or <8 x i64> %4, %3 %5 = or <8 x i64> %4, %3
ret <8 x i64> %5 ret <8 x i64> %5
} }
define <8 x i64> @bitselect_v8i64_rm(<8 x i64>, <8 x i64>* nocapture readonly) { define <8 x i64> @bitselect_v8i64_rm(<8 x i64>, <8 x i64>* nocapture readonly) {
; SSE-LABEL: bitselect_v8i64_rm: ; SSE-LABEL: bitselect_v8i64_rm:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm4 = [8589934593,3]
; SSE-NEXT: andps %xmm4, %xmm3
; SSE-NEXT: andps %xmm4, %xmm2
; SSE-NEXT: andps %xmm4, %xmm1
; SSE-NEXT: andps %xmm4, %xmm0
; SSE-NEXT: movaps {{.*#+}} xmm4 = [18446744065119617022,18446744073709551612] ; SSE-NEXT: movaps {{.*#+}} xmm4 = [18446744065119617022,18446744073709551612]
; SSE-NEXT: movaps 48(%rdi), %xmm5 ; SSE-NEXT: movaps 48(%rdi), %xmm8
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: andps %xmm4, %xmm8
; SSE-NEXT: orps %xmm5, %xmm3 ; SSE-NEXT: movaps 32(%rdi), %xmm9
; SSE-NEXT: movaps 32(%rdi), %xmm5 ; SSE-NEXT: andps %xmm4, %xmm9
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: movaps 16(%rdi), %xmm7
; SSE-NEXT: orps %xmm5, %xmm2 ; SSE-NEXT: andps %xmm4, %xmm7
; SSE-NEXT: movaps 16(%rdi), %xmm5 ; SSE-NEXT: movaps (%rdi), %xmm6
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: andps %xmm4, %xmm6
; SSE-NEXT: orps %xmm5, %xmm1 ; SSE-NEXT: movaps %xmm4, %xmm5
; SSE-NEXT: andps (%rdi), %xmm4 ; SSE-NEXT: andnps %xmm0, %xmm5
; SSE-NEXT: orps %xmm4, %xmm0 ; SSE-NEXT: orps %xmm6, %xmm5
; SSE-NEXT: movaps %xmm4, %xmm6
; SSE-NEXT: andnps %xmm1, %xmm6
; SSE-NEXT: orps %xmm7, %xmm6
; SSE-NEXT: movaps %xmm4, %xmm7
; SSE-NEXT: andnps %xmm2, %xmm7
; SSE-NEXT: orps %xmm9, %xmm7
; SSE-NEXT: andnps %xmm3, %xmm4
; SSE-NEXT: orps %xmm8, %xmm4
; SSE-NEXT: movaps %xmm5, %xmm0
; SSE-NEXT: movaps %xmm6, %xmm1
; SSE-NEXT: movaps %xmm7, %xmm2
; SSE-NEXT: movaps %xmm4, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v8i64_rm: ; XOP-LABEL: bitselect_v8i64_rm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [8589934593,3,8589934593,3] ; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [8589934593,3,8589934593,3]
; XOP-NEXT: # ymm2 = mem[0,1,0,1] ; XOP-NEXT: # ymm2 = mem[0,1,0,1]
; XOP-NEXT: vandps %ymm2, %ymm1, %ymm1 ; XOP-NEXT: vandps %ymm2, %ymm1, %ymm1
; XOP-NEXT: vandps %ymm2, %ymm0, %ymm0 ; XOP-NEXT: vandps %ymm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; AVX512F-NEXT: retq
%6 = or <8 x i64> %5, %4 %6 = or <8 x i64> %5, %4
ret <8 x i64> %6 ret <8 x i64> %6
} }
define <8 x i64> @bitselect_v8i64_mr(<8 x i64>* nocapture readonly, <8 x i64>) { define <8 x i64> @bitselect_v8i64_mr(<8 x i64>* nocapture readonly, <8 x i64>) {
; SSE-LABEL: bitselect_v8i64_mr: ; SSE-LABEL: bitselect_v8i64_mr:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm4 = [12884901890,4294967296] ; SSE-NEXT: movaps {{.*#+}} xmm4 = [12884901890,4294967296]
; SSE-NEXT: movaps 48(%rdi), %xmm5 ; SSE-NEXT: movaps 48(%rdi), %xmm8
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: andps %xmm4, %xmm8
; SSE-NEXT: movaps 32(%rdi), %xmm6 ; SSE-NEXT: movaps 32(%rdi), %xmm9
; SSE-NEXT: andps %xmm4, %xmm6 ; SSE-NEXT: andps %xmm4, %xmm9
; SSE-NEXT: movaps 16(%rdi), %xmm7 ; SSE-NEXT: movaps 16(%rdi), %xmm7
; SSE-NEXT: andps %xmm4, %xmm7 ; SSE-NEXT: andps %xmm4, %xmm7
; SSE-NEXT: andps (%rdi), %xmm4 ; SSE-NEXT: movaps (%rdi), %xmm6
; SSE-NEXT: movaps {{.*#+}} xmm8 = [18446744060824649725,18446744069414584319] ; SSE-NEXT: andps %xmm4, %xmm6
; SSE-NEXT: andps %xmm8, %xmm3 ; SSE-NEXT: movaps %xmm4, %xmm5
; SSE-NEXT: orps %xmm5, %xmm3 ; SSE-NEXT: andnps %xmm0, %xmm5
; SSE-NEXT: andps %xmm8, %xmm2 ; SSE-NEXT: orps %xmm6, %xmm5
; SSE-NEXT: orps %xmm6, %xmm2 ; SSE-NEXT: movaps %xmm4, %xmm6
; SSE-NEXT: andps %xmm8, %xmm1 ; SSE-NEXT: andnps %xmm1, %xmm6
; SSE-NEXT: orps %xmm7, %xmm1 ; SSE-NEXT: orps %xmm7, %xmm6
; SSE-NEXT: andps %xmm8, %xmm0 ; SSE-NEXT: movaps %xmm4, %xmm7
; SSE-NEXT: orps %xmm4, %xmm0 ; SSE-NEXT: andnps %xmm2, %xmm7
; SSE-NEXT: orps %xmm9, %xmm7
; SSE-NEXT: andnps %xmm3, %xmm4
; SSE-NEXT: orps %xmm8, %xmm4
; SSE-NEXT: movaps %xmm5, %xmm0
; SSE-NEXT: movaps %xmm6, %xmm1
; SSE-NEXT: movaps %xmm7, %xmm2
; SSE-NEXT: movaps %xmm4, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v8i64_mr: ; XOP-LABEL: bitselect_v8i64_mr:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [12884901890,4294967296,12884901890,4294967296] ; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [12884901890,4294967296,12884901890,4294967296]
; XOP-NEXT: # ymm2 = mem[0,1,0,1] ; XOP-NEXT: # ymm2 = mem[0,1,0,1]
; XOP-NEXT: vandps 32(%rdi), %ymm2, %ymm3 ; XOP-NEXT: vandps 32(%rdi), %ymm2, %ymm3
; XOP-NEXT: vandps (%rdi), %ymm2, %ymm2 ; XOP-NEXT: vandps (%rdi), %ymm2, %ymm2
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; AVX512F-NEXT: retq
%5 = and <8 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297> %5 = and <8 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297>
%6 = or <8 x i64> %4, %5 %6 = or <8 x i64> %4, %5
ret <8 x i64> %6 ret <8 x i64> %6
} }
define <8 x i64> @bitselect_v8i64_mm(<8 x i64>* nocapture readonly, <8 x i64>* nocapture readonly) { define <8 x i64> @bitselect_v8i64_mm(<8 x i64>* nocapture readonly, <8 x i64>* nocapture readonly) {
; SSE-LABEL: bitselect_v8i64_mm: ; SSE-LABEL: bitselect_v8i64_mm:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm4 = [3,8589934593] ; SSE-NEXT: movaps {{.*#+}} xmm3 = [18446744073709551612,18446744065119617022]
; SSE-NEXT: movaps 48(%rdi), %xmm1 ; SSE-NEXT: movaps 48(%rsi), %xmm4
; SSE-NEXT: andps %xmm4, %xmm1 ; SSE-NEXT: andps %xmm3, %xmm4
; SSE-NEXT: movaps 32(%rdi), %xmm5 ; SSE-NEXT: movaps 32(%rsi), %xmm5
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: andps %xmm3, %xmm5
; SSE-NEXT: movaps 16(%rdi), %xmm6 ; SSE-NEXT: movaps 16(%rsi), %xmm2
; SSE-NEXT: andps %xmm4, %xmm6 ; SSE-NEXT: andps %xmm3, %xmm2
; SSE-NEXT: andps (%rdi), %xmm4 ; SSE-NEXT: movaps (%rsi), %xmm1
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551612,18446744065119617022] ; SSE-NEXT: andps %xmm3, %xmm1
; SSE-NEXT: movaps 48(%rsi), %xmm3 ; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: andps %xmm0, %xmm3 ; SSE-NEXT: andnps (%rdi), %xmm0
; SSE-NEXT: orps %xmm1, %xmm3 ; SSE-NEXT: orps %xmm1, %xmm0
; SSE-NEXT: movaps 32(%rsi), %xmm2 ; SSE-NEXT: movaps %xmm3, %xmm1
; SSE-NEXT: andps %xmm0, %xmm2 ; SSE-NEXT: andnps 16(%rdi), %xmm1
; SSE-NEXT: orps %xmm2, %xmm1
; SSE-NEXT: movaps %xmm3, %xmm2
; SSE-NEXT: andnps 32(%rdi), %xmm2
; SSE-NEXT: orps %xmm5, %xmm2 ; SSE-NEXT: orps %xmm5, %xmm2
; SSE-NEXT: movaps 16(%rsi), %xmm1 ; SSE-NEXT: andnps 48(%rdi), %xmm3
; SSE-NEXT: andps %xmm0, %xmm1 ; SSE-NEXT: orps %xmm4, %xmm3
; SSE-NEXT: orps %xmm6, %xmm1
; SSE-NEXT: andps (%rsi), %xmm0
; SSE-NEXT: orps %xmm4, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v8i64_mm: ; XOP-LABEL: bitselect_v8i64_mm:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm0 = [3,8589934593,3,8589934593] ; XOP-NEXT: vbroadcastf128 {{.*#+}} ymm0 = [3,8589934593,3,8589934593]
; XOP-NEXT: # ymm0 = mem[0,1,0,1] ; XOP-NEXT: # ymm0 = mem[0,1,0,1]
; XOP-NEXT: vandps 32(%rdi), %ymm0, %ymm1 ; XOP-NEXT: vandps 32(%rdi), %ymm0, %ymm1
; XOP-NEXT: vandps (%rdi), %ymm0, %ymm0 ; XOP-NEXT: vandps (%rdi), %ymm0, %ymm0
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/combine-fcopysign.ll

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret <4 x float> %2 ret <4 x float> %2
} }
; copysign(x, fp_extend(y)) -> copysign(x, y) ; copysign(x, fp_extend(y)) -> copysign(x, y)
define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) { define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) {
; SSE-LABEL: combine_vec_fcopysign_fpext_sgn: ; SSE-LABEL: combine_vec_fcopysign_fpext_sgn:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm2, %xmm3 ; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: cvtss2sd %xmm2, %xmm4 ; SSE-NEXT: movshdup {{.*#+}} xmm4 = xmm2[1,1,3,3]
; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm2[1,1,3,3] ; SSE-NEXT: cvtss2sd %xmm2, %xmm5
; SSE-NEXT: movaps %xmm2, %xmm6 ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1] ; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm2[2,3] ; SSE-NEXT: movaps {{.*#+}} xmm6
; SSE-NEXT: movaps {{.*#+}} xmm7
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: andps %xmm7, %xmm2
; SSE-NEXT: movaps {{.*#+}} xmm8 = [-0.0E+0,-0.0E+0]
; SSE-NEXT: andps %xmm8, %xmm4
; SSE-NEXT: orps %xmm4, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: andps %xmm7, %xmm0
; SSE-NEXT: xorps %xmm4, %xmm4
; SSE-NEXT: cvtss2sd %xmm5, %xmm4
; SSE-NEXT: andps %xmm8, %xmm4
; SSE-NEXT: orps %xmm0, %xmm4
; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: andps %xmm7, %xmm0
; SSE-NEXT: cvtss2sd %xmm3, %xmm3 ; SSE-NEXT: cvtss2sd %xmm3, %xmm3
; SSE-NEXT: andps %xmm8, %xmm3 ; SSE-NEXT: movaps %xmm6, %xmm7
; SSE-NEXT: orps %xmm0, %xmm3 ; SSE-NEXT: andnps %xmm3, %xmm7
; SSE-NEXT: andps %xmm7, %xmm1 ; SSE-NEXT: movaps %xmm1, %xmm3
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
; SSE-NEXT: cvtss2sd %xmm6, %xmm0 ; SSE-NEXT: andps %xmm6, %xmm3
; SSE-NEXT: andps %xmm8, %xmm0 ; SSE-NEXT: orps %xmm3, %xmm7
; SSE-NEXT: orps %xmm0, %xmm1 ; SSE-NEXT: andps %xmm6, %xmm1
; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE-NEXT: cvtss2sd %xmm2, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: movaps %xmm6, %xmm3
; SSE-NEXT: andnps %xmm2, %xmm3
; SSE-NEXT: orps %xmm3, %xmm1
; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm7[0]
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE-NEXT: andps %xmm6, %xmm2
; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: cvtss2sd %xmm4, %xmm3
; SSE-NEXT: andps %xmm6, %xmm0
; SSE-NEXT: andnps %xmm3, %xmm6
; SSE-NEXT: orps %xmm2, %xmm6
; SSE-NEXT: andps {{.*}}(%rip), %xmm5
; SSE-NEXT: orps %xmm5, %xmm0
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm6[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_vec_fcopysign_fpext_sgn: ; AVX-LABEL: combine_vec_fcopysign_fpext_sgn:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2 ; AVX-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2
; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; AVX-NEXT: vcvtps2pd %xmm1, %ymm1 ; AVX-NEXT: vcvtps2pd %xmm1, %ymm1
; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = fpext <4 x float> %y to <4 x double> %1 = fpext <4 x float> %y to <4 x double>
%2 = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %1) %2 = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %1)
ret <4 x double> %2 ret <4 x double> %2
} }
; copysign(x, fp_round(y)) -> copysign(x, y) ; copysign(x, fp_round(y)) -> copysign(x, y)
define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x double> %y) { define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x double> %y) {
; SSE-LABEL: combine_vec_fcopysign_fptrunc_sgn: ; SSE-LABEL: combine_vec_fcopysign_fptrunc_sgn:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm3 ; SSE-NEXT: movaps %xmm0, %xmm3
; SSE-NEXT: movaps {{.*#+}} xmm5 ; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm0[1]
; SSE-NEXT: andps %xmm5, %xmm0 ; SSE-NEXT: movaps {{.*#+}} xmm4
; SSE-NEXT: cvtsd2ss %xmm1, %xmm6 ; SSE-NEXT: andps %xmm4, %xmm3
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; SSE-NEXT: cvtsd2ss %xmm2, %xmm5
; SSE-NEXT: andps %xmm4, %xmm6 ; SSE-NEXT: movaps %xmm4, %xmm6
; SSE-NEXT: orps %xmm6, %xmm0 ; SSE-NEXT: andnps %xmm5, %xmm6
; SSE-NEXT: movshdup {{.*#+}} xmm6 = xmm3[1,1,3,3] ; SSE-NEXT: orps %xmm3, %xmm6
; SSE-NEXT: andps %xmm5, %xmm6 ; SSE-NEXT: movaps %xmm0, %xmm3
; SSE-NEXT: andps %xmm4, %xmm3
; SSE-NEXT: xorps %xmm5, %xmm5
; SSE-NEXT: cvtsd2ss %xmm1, %xmm5
; SSE-NEXT: movaps %xmm4, %xmm7
; SSE-NEXT: andnps %xmm5, %xmm7
; SSE-NEXT: orps %xmm7, %xmm3
; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
; SSE-NEXT: andps %xmm4, %xmm5
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: cvtsd2ss %xmm1, %xmm1 ; SSE-NEXT: cvtsd2ss %xmm1, %xmm1
; SSE-NEXT: andps %xmm4, %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: orps %xmm6, %xmm1 ; SSE-NEXT: orps %xmm5, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE-NEXT: movaps %xmm3, %xmm1 ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm6[0],xmm3[3]
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE-NEXT: andps %xmm5, %xmm1 ; SSE-NEXT: andps %xmm4, %xmm0
; SSE-NEXT: xorps %xmm6, %xmm6
; SSE-NEXT: cvtsd2ss %xmm2, %xmm6
; SSE-NEXT: andps %xmm4, %xmm6
; SSE-NEXT: orps %xmm1, %xmm6
; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm6[0],xmm0[3]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE-NEXT: andps %xmm5, %xmm3
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsd2ss %xmm2, %xmm1 ; SSE-NEXT: cvtsd2ss %xmm2, %xmm1
; SSE-NEXT: andps %xmm4, %xmm1 ; SSE-NEXT: andnps %xmm1, %xmm4
; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm0, %xmm4
; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_vec_fcopysign_fptrunc_sgn: ; AVX-LABEL: combine_vec_fcopysign_fptrunc_sgn:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm2 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm2
; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1 ; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1
; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] ; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
Show All 12 Lines

llvm/trunk/test/CodeGen/X86/vec-copysign.ll

; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 --check-prefix=CHECK ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=CHECK ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
; Assertions have been enhanced from utils/update_llc_test_checks.py to show the constant pool values. ; Assertions have been enhanced from utils/update_llc_test_checks.py to show the constant pool values.
; Use a macosx triple to make sure the format of those constant strings is exact. ; Use a macosx triple to make sure the format of those constant strings is exact.
; CHECK: [[SIGNMASK1:L.+]]: ; CHECK: [[SIGNMASK1:L.+]]:
; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 2147483648 ; CHECK-NEXT: .long 2147483648
Show All 19 Lines
; AVX-NEXT: vandps [[MAGMASK1]](%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps [[MAGMASK1]](%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
%tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b ) %tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
ret <4 x float> %tmp ret <4 x float> %tmp
} }
; SSE2: [[SIGNMASK2:L.+]]:
; SSE2-NEXT: .long 2147483648
; SSE2-NEXT: .long 2147483648
; SSE2-NEXT: .long 2147483648
; SSE2-NEXT: .long 2147483648
; SSE2: [[MAGMASK2:L.+]]: ; SSE2: [[MAGMASK2:L.+]]:
; SSE2-NEXT: .long 2147483647 ; SSE2-NEXT: .long 2147483647
; SSE2-NEXT: .long 2147483647 ; SSE2-NEXT: .long 2147483647
; SSE2-NEXT: .long 2147483647 ; SSE2-NEXT: .long 2147483647
; SSE2-NEXT: .long 2147483647 ; SSE2-NEXT: .long 2147483647
; AVX: [[SIGNMASK2:L.+]]: ; AVX: [[SIGNMASK2:L.+]]:
; AVX-NEXT: .long 2147483648 ; AVX-NEXT: .long 2147483648
Show All 13 Lines
; AVX-NEXT: .long 2147483647 ; AVX-NEXT: .long 2147483647
; AVX-NEXT: .long 2147483647 ; AVX-NEXT: .long 2147483647
; AVX-NEXT: .long 2147483647 ; AVX-NEXT: .long 2147483647
; AVX-NEXT: .long 2147483647 ; AVX-NEXT: .long 2147483647
define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind { define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
; SSE2-LABEL: v8f32: ; SSE2-LABEL: v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps [[SIGNMASK2]](%rip), %xmm4 ; SSE2-NEXT: movaps [[MAGMASK2]](%rip), %xmm4
; SSE2-NEXT: andps %xmm4, %xmm2 ; SSE2-NEXT: movaps %xmm4, %xmm5
; SSE2-NEXT: movaps [[MAGMASK2]](%rip), %xmm5 ; SSE2-NEXT: andnps %xmm2, %xmm5
; SSE2-NEXT: andps %xmm5, %xmm0 ; SSE2-NEXT: andps %xmm4, %xmm0
; SSE2-NEXT: orps %xmm2, %xmm0 ; SSE2-NEXT: orps %xmm5, %xmm0
; SSE2-NEXT: andps %xmm4, %xmm3 ; SSE2-NEXT: andps %xmm4, %xmm1
; SSE2-NEXT: andps %xmm5, %xmm1 ; SSE2-NEXT: andnps %xmm3, %xmm4
; SSE2-NEXT: orps %xmm3, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: v8f32: ; AVX-LABEL: v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vandps [[SIGNMASK2]](%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps [[SIGNMASK2]](%rip), %ymm1, %ymm1
; AVX-NEXT: vandps [[MAGMASK2]](%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps [[MAGMASK2]](%rip), %ymm0, %ymm0
; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
Show All 24 Lines
; AVX-NEXT: vandps [[MAGMASK3]](%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps [[MAGMASK3]](%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b ) %tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
ret <2 x double> %tmp ret <2 x double> %tmp
} }
; SSE2: [[SIGNMASK4:L.+]]:
; SSE2-NEXT: .quad -9223372036854775808
; SSE2-NEXT: .quad -9223372036854775808
; SSE2: [[MAGMASK4:L.+]]: ; SSE2: [[MAGMASK4:L.+]]:
; SSE2-NEXT: .quad 9223372036854775807 ; SSE2-NEXT: .quad 9223372036854775807
; SSE2-NEXT: .quad 9223372036854775807 ; SSE2-NEXT: .quad 9223372036854775807
; AVX: [[SIGNMASK4:L.+]]: ; AVX: [[SIGNMASK4:L.+]]:
; AVX-NEXT: .quad -9223372036854775808 ; AVX-NEXT: .quad -9223372036854775808
; AVX-NEXT: .quad -9223372036854775808 ; AVX-NEXT: .quad -9223372036854775808
; AVX-NEXT: .quad -9223372036854775808 ; AVX-NEXT: .quad -9223372036854775808
; AVX-NEXT: .quad -9223372036854775808 ; AVX-NEXT: .quad -9223372036854775808
; AVX: [[MAGMASK4:L.+]]: ; AVX: [[MAGMASK4:L.+]]:
; AVX-NEXT: .quad 9223372036854775807 ; AVX-NEXT: .quad 9223372036854775807
; AVX-NEXT: .quad 9223372036854775807 ; AVX-NEXT: .quad 9223372036854775807
; AVX-NEXT: .quad 9223372036854775807 ; AVX-NEXT: .quad 9223372036854775807
; AVX-NEXT: .quad 9223372036854775807 ; AVX-NEXT: .quad 9223372036854775807
define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind { define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
; SSE2-LABEL: v4f64: ; SSE2-LABEL: v4f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps [[SIGNMASK4]](%rip), %xmm4 ; SSE2-NEXT: movaps [[MAGMASK4]](%rip), %xmm4
; SSE2-NEXT: andps %xmm4, %xmm2 ; SSE2-NEXT: movaps %xmm4, %xmm5
; SSE2-NEXT: movaps [[MAGMASK4]](%rip), %xmm5 ; SSE2-NEXT: andnps %xmm2, %xmm5
; SSE2-NEXT: andps %xmm5, %xmm0 ; SSE2-NEXT: andps %xmm4, %xmm0
; SSE2-NEXT: orps %xmm2, %xmm0 ; SSE2-NEXT: orps %xmm5, %xmm0
; SSE2-NEXT: andps %xmm4, %xmm3 ; SSE2-NEXT: andps %xmm4, %xmm1
; SSE2-NEXT: andps %xmm5, %xmm1 ; SSE2-NEXT: andnps %xmm3, %xmm4
; SSE2-NEXT: orps %xmm3, %xmm1 ; SSE2-NEXT: orps %xmm4, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX-LABEL: v4f64: ; AVX-LABEL: v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vandps [[SIGNMASK4]](%rip), %ymm1, %ymm1 ; AVX-NEXT: vandps [[SIGNMASK4]](%rip), %ymm1, %ymm1
; AVX-NEXT: vandps [[MAGMASK4]](%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps [[MAGMASK4]](%rip), %ymm0, %ymm0
; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
Show All 10 Lines

llvm/trunk/test/CodeGen/X86/vector-bitreverse.ll

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
; XOP-NEXT: retq ; XOP-NEXT: retq
%b = call i64 @llvm.bitreverse.i64(i64 %a) %b = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %b ret i64 %b
} }
define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind { define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v16i8: ; SSE2-LABEL: test_bitreverse_v16i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psllw $4, %xmm2 ; SSE2-NEXT: psllw $4, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1 ; SSE2-NEXT: psllw $2, %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psllw $4, %xmm2 ; SSE2-NEXT: psllw $4, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1 ; SSE2-NEXT: psllw $2, %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psllw $4, %xmm2 ; SSE2-NEXT: psllw $4, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1 ; SSE2-NEXT: psllw $2, %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm2, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psllw $4, %xmm2 ; SSE2-NEXT: psllw $4, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pandn %xmm2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: psllw $2, %xmm1 ; SSE2-NEXT: psllw $2, %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; XOP-NEXT: retq ; XOP-NEXT: retq
%b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a) %b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)
ret <2 x i64> %b ret <2 x i64> %b
} }
define <32 x i8> @test_bitreverse_v32i8(<32 x i8> %a) nounwind { define <32 x i8> @test_bitreverse_v32i8(<32 x i8> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v32i8: ; SSE2-LABEL: test_bitreverse_v32i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $4, %xmm3 ; SSE2-NEXT: psllw $4, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm3 ; SSE2-NEXT: pandn %xmm3, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pand %xmm3, %xmm4 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $2, %xmm4 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm8, %xmm4 ; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm11, %xmm0
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm4, %xmm7 ; SSE2-NEXT: pand %xmm4, %xmm5
; SSE2-NEXT: psrlw $1, %xmm7 ; SSE2-NEXT: psrlw $1, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm11, %xmm7 ; SSE2-NEXT: pand %xmm6, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm7 ; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: pand %xmm2, %xmm7 ; SSE2-NEXT: pand %xmm1, %xmm5
; SSE2-NEXT: psllw $4, %xmm7 ; SSE2-NEXT: psllw $4, %xmm5
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: pand %xmm5, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm5, %xmm1
; SSE2-NEXT: por %xmm7, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $2, %xmm3 ; SSE2-NEXT: psllw $2, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pand %xmm9, %xmm3
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: psrlw $1, %xmm4 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm11, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: pand %xmm7, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: test_bitreverse_v32i8: ; SSSE3-LABEL: test_bitreverse_v32i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a) %b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a)
ret <32 x i8> %b ret <32 x i8> %b
} }
define <16 x i16> @test_bitreverse_v16i16(<16 x i16> %a) nounwind { define <16 x i16> @test_bitreverse_v16i16(<16 x i16> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v16i16: ; SSE2-LABEL: test_bitreverse_v16i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm4[8],xmm2[9],xmm4[9],xmm2[10],xmm4[10],xmm2[11],xmm4[11],xmm2[12],xmm4[12],xmm2[13],xmm4[13],xmm2[14],xmm4[14],xmm2[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $4, %xmm3 ; SSE2-NEXT: psllw $4, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm3 ; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm11, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: psrlw $1, %xmm7 ; SSE2-NEXT: psrlw $1, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm11, %xmm7 ; SSE2-NEXT: pand %xmm12, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm12, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm7 ; SSE2-NEXT: movdqa %xmm2, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm7 = xmm7[8],xmm4[8],xmm7[9],xmm4[9],xmm7[10],xmm4[10],xmm7[11],xmm4[11],xmm7[12],xmm4[12],xmm7[13],xmm4[13],xmm7[14],xmm4[14],xmm7[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm4[8],xmm6[9],xmm4[9],xmm6[10],xmm4[10],xmm6[11],xmm4[11],xmm6[12],xmm4[12],xmm6[13],xmm4[13],xmm6[14],xmm4[14],xmm6[15],xmm4[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm7 = xmm7[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm7 = xmm7[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm7, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm4, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $2, %xmm3 ; SSE2-NEXT: psllw $2, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pand %xmm9, %xmm3
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm5 ; SSE2-NEXT: pand %xmm1, %xmm5
; SSE2-NEXT: psrlw $1, %xmm5 ; SSE2-NEXT: psrlw $1, %xmm5
; SSE2-NEXT: pand %xmm11, %xmm5 ; SSE2-NEXT: pand %xmm12, %xmm5
; SSE2-NEXT: pand %xmm12, %xmm1 ; SSE2-NEXT: pand %xmm7, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: test_bitreverse_v16i16: ; SSSE3-LABEL: test_bitreverse_v16i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
; SSSE3-NEXT: pshufb %xmm4, %xmm0 ; SSSE3-NEXT: pshufb %xmm4, %xmm0
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a) %b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)
ret <16 x i16> %b ret <16 x i16> %b
} }
define <8 x i32> @test_bitreverse_v8i32(<8 x i32> %a) nounwind { define <8 x i32> @test_bitreverse_v8i32(<8 x i32> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v8i32: ; SSE2-LABEL: test_bitreverse_v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm4[8],xmm2[9],xmm4[9],xmm2[10],xmm4[10],xmm2[11],xmm4[11],xmm2[12],xmm4[12],xmm2[13],xmm4[13],xmm2[14],xmm4[14],xmm2[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $4, %xmm3 ; SSE2-NEXT: psllw $4, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm3 ; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm11, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: psrlw $1, %xmm7 ; SSE2-NEXT: psrlw $1, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm11, %xmm7 ; SSE2-NEXT: pand %xmm12, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm12, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm7 ; SSE2-NEXT: movdqa %xmm2, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm7 = xmm7[8],xmm4[8],xmm7[9],xmm4[9],xmm7[10],xmm4[10],xmm7[11],xmm4[11],xmm7[12],xmm4[12],xmm7[13],xmm4[13],xmm7[14],xmm4[14],xmm7[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm4[8],xmm6[9],xmm4[9],xmm6[10],xmm4[10],xmm6[11],xmm4[11],xmm6[12],xmm4[12],xmm6[13],xmm4[13],xmm6[14],xmm4[14],xmm6[15],xmm4[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm7 = xmm7[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm7 = xmm7[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm7, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm4, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $2, %xmm3 ; SSE2-NEXT: psllw $2, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pand %xmm9, %xmm3
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm5 ; SSE2-NEXT: pand %xmm1, %xmm5
; SSE2-NEXT: psrlw $1, %xmm5 ; SSE2-NEXT: psrlw $1, %xmm5
; SSE2-NEXT: pand %xmm11, %xmm5 ; SSE2-NEXT: pand %xmm12, %xmm5
; SSE2-NEXT: pand %xmm12, %xmm1 ; SSE2-NEXT: pand %xmm7, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: test_bitreverse_v8i32: ; SSSE3-LABEL: test_bitreverse_v8i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
; SSSE3-NEXT: pshufb %xmm4, %xmm0 ; SSSE3-NEXT: pshufb %xmm4, %xmm0
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a) %b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
ret <8 x i32> %b ret <8 x i32> %b
} }
define <4 x i64> @test_bitreverse_v4i64(<4 x i64> %a) nounwind { define <4 x i64> @test_bitreverse_v4i64(<4 x i64> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v4i64: ; SSE2-LABEL: test_bitreverse_v4i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm4[8],xmm2[9],xmm4[9],xmm2[10],xmm4[10],xmm2[11],xmm4[11],xmm2[12],xmm4[12],xmm2[13],xmm4[13],xmm2[14],xmm4[14],xmm2[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $4, %xmm3 ; SSE2-NEXT: psllw $4, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm3 ; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm11, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: psrlw $1, %xmm7 ; SSE2-NEXT: psrlw $1, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm11, %xmm7 ; SSE2-NEXT: pand %xmm12, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm12, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm7 ; SSE2-NEXT: movdqa %xmm2, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm7 = xmm7[8],xmm4[8],xmm7[9],xmm4[9],xmm7[10],xmm4[10],xmm7[11],xmm4[11],xmm7[12],xmm4[12],xmm7[13],xmm4[13],xmm7[14],xmm4[14],xmm7[15],xmm4[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm4[8],xmm6[9],xmm4[9],xmm6[10],xmm4[10],xmm6[11],xmm4[11],xmm6[12],xmm4[12],xmm6[13],xmm4[13],xmm6[14],xmm4[14],xmm6[15],xmm4[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm7 = xmm7[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm7 = xmm7[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm7, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm4, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psllw $2, %xmm3 ; SSE2-NEXT: psllw $2, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pand %xmm9, %xmm3
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm5 ; SSE2-NEXT: pand %xmm1, %xmm5
; SSE2-NEXT: psrlw $1, %xmm5 ; SSE2-NEXT: psrlw $1, %xmm5
; SSE2-NEXT: pand %xmm11, %xmm5 ; SSE2-NEXT: pand %xmm12, %xmm5
; SSE2-NEXT: pand %xmm12, %xmm1 ; SSE2-NEXT: pand %xmm7, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: test_bitreverse_v4i64: ; SSSE3-LABEL: test_bitreverse_v4i64:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8]
; SSSE3-NEXT: pshufb %xmm4, %xmm0 ; SSSE3-NEXT: pshufb %xmm4, %xmm0
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a) %b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
ret <4 x i64> %b ret <4 x i64> %b
} }
define <64 x i8> @test_bitreverse_v64i8(<64 x i8> %a) nounwind { define <64 x i8> @test_bitreverse_v64i8(<64 x i8> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v64i8: ; SSE2-LABEL: test_bitreverse_v64i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm13 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa %xmm3, %xmm14
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm13, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $4, %xmm5 ; SSE2-NEXT: psllw $4, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm7, %xmm5 ; SSE2-NEXT: pandn %xmm5, %xmm6
; SSE2-NEXT: pand %xmm7, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm13, %xmm0 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm6 ; SSE2-NEXT: movdqa %xmm0, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: psllw $2, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm8, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm9, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
; SSE2-NEXT: pand %xmm11, %xmm0
; SSE2-NEXT: por %xmm6, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170]
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm7
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm7
; SSE2-NEXT: psrlw $1, %xmm4 ; SSE2-NEXT: psrlw $1, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm11, %xmm4 ; SSE2-NEXT: pand %xmm12, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm12 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; SSE2-NEXT: movdqa {{.*#+}} xmm13 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; SSE2-NEXT: pand %xmm12, %xmm0 ; SSE2-NEXT: pand %xmm13, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm1, %xmm7
; SSE2-NEXT: pand %xmm13, %xmm4 ; SSE2-NEXT: pand %xmm3, %xmm7
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm7
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm1 ; SSE2-NEXT: pandn %xmm7, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm13, %xmm1 ; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm4 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm4 ; SSE2-NEXT: pand %xmm8, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm4
; SSE2-NEXT: psrlw $1, %xmm4 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm11, %xmm4 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm1 ; SSE2-NEXT: pand %xmm13, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm4 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: movdqa %xmm3, %xmm7
; SSE2-NEXT: pand %xmm7, %xmm2 ; SSE2-NEXT: pandn %xmm4, %xmm7
; SSE2-NEXT: pand %xmm9, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2 ; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm13, %xmm2 ; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: por %xmm4, %xmm2 ; SSE2-NEXT: por %xmm7, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm4 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm4 ; SSE2-NEXT: pand %xmm8, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2
; SSE2-NEXT: pand %xmm10, %xmm2 ; SSE2-NEXT: pand %xmm10, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2
; SSE2-NEXT: pand %xmm11, %xmm2
; SSE2-NEXT: por %xmm4, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm4 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm4
; SSE2-NEXT: psrlw $1, %xmm4 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm11, %xmm4 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm2 ; SSE2-NEXT: pand %xmm13, %xmm2
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: por %xmm4, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm14, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm4 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $4, %xmm4 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: pand %xmm9, %xmm14
; SSE2-NEXT: pand %xmm7, %xmm3 ; SSE2-NEXT: psrlw $4, %xmm14
; SSE2-NEXT: psrlw $4, %xmm3 ; SSE2-NEXT: pand %xmm3, %xmm14
; SSE2-NEXT: pand %xmm13, %xmm3 ; SSE2-NEXT: pandn %xmm4, %xmm3
; SSE2-NEXT: por %xmm4, %xmm3 ; SSE2-NEXT: por %xmm14, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm8, %xmm5
; SSE2-NEXT: pand %xmm9, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm10, %xmm3 ; SSE2-NEXT: pand %xmm10, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm11, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3 ; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm6
; SSE2-NEXT: pand %xmm11, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm6
; SSE2-NEXT: pand %xmm12, %xmm3 ; SSE2-NEXT: pand %xmm13, %xmm3
; SSE2-NEXT: paddb %xmm3, %xmm3 ; SSE2-NEXT: paddb %xmm3, %xmm3
; SSE2-NEXT: por %xmm6, %xmm3 ; SSE2-NEXT: por %xmm6, %xmm3
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: test_bitreverse_v64i8: ; SSSE3-LABEL: test_bitreverse_v64i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa %xmm0, %xmm5 ; SSSE3-NEXT: movdqa %xmm0, %xmm5
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %a) %b = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %a)
ret <64 x i8> %b ret <64 x i8> %b
} }
define <32 x i16> @test_bitreverse_v32i16(<32 x i16> %a) nounwind { define <32 x i16> @test_bitreverse_v32i16(<32 x i16> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v32i16: ; SSE2-LABEL: test_bitreverse_v32i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm3, %xmm15
; SSE2-NEXT: pxor %xmm14, %xmm14 ; SSE2-NEXT: pxor %xmm14, %xmm14
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm14[8],xmm3[9],xmm14[9],xmm3[10],xmm14[10],xmm3[11],xmm14[11],xmm3[12],xmm14[12],xmm3[13],xmm14[13],xmm3[14],xmm14[14],xmm3[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm4, %xmm0 ; SSE2-NEXT: packuswb %xmm3, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $4, %xmm5 ; SSE2-NEXT: psllw $4, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm3, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm5 ; SSE2-NEXT: pandn %xmm5, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm7
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm7
; SSE2-NEXT: psllw $2, %xmm7 ; SSE2-NEXT: psllw $2, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm9, %xmm7 ; SSE2-NEXT: pand %xmm9, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
Show All 15 Lines
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm6, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm8, %xmm1 ; SSE2-NEXT: pand %xmm8, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1 ; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm1 ; SSE2-NEXT: pand %xmm13, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6]
; SSE2-NEXT: packuswb %xmm6, %xmm2 ; SSE2-NEXT: packuswb %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pandn %xmm4, %xmm6
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm2 ; SSE2-NEXT: pand %xmm10, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm2
; SSE2-NEXT: pand %xmm11, %xmm2 ; SSE2-NEXT: pand %xmm11, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm2 ; SSE2-NEXT: pand %xmm13, %xmm2
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: movdqa %xmm15, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm15[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1],xmm3[2],xmm14[2],xmm3[3],xmm14[3],xmm3[4],xmm14[4],xmm3[5],xmm14[5],xmm3[6],xmm14[6],xmm3[7],xmm14[7] ; SSE2-NEXT: packuswb %xmm4, %xmm6
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7] ; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6] ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: packuswb %xmm6, %xmm3 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm8, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psrlw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm3 ; SSE2-NEXT: pandn %xmm4, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3
; SSE2-NEXT: por %xmm6, %xmm3 ; SSE2-NEXT: por %xmm6, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: pand %xmm9, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: pand %xmm10, %xmm3 ; SSE2-NEXT: pand %xmm10, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm11, %xmm3 ; SSE2-NEXT: pand %xmm11, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3 ; SSE2-NEXT: por %xmm5, %xmm3
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a) %b = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
ret <32 x i16> %b ret <32 x i16> %b
} }
define <16 x i32> @test_bitreverse_v16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_bitreverse_v16i32(<16 x i32> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v16i32: ; SSE2-LABEL: test_bitreverse_v16i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm3, %xmm15
; SSE2-NEXT: pxor %xmm14, %xmm14 ; SSE2-NEXT: pxor %xmm14, %xmm14
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm14[8],xmm3[9],xmm14[9],xmm3[10],xmm14[10],xmm3[11],xmm14[11],xmm3[12],xmm14[12],xmm3[13],xmm14[13],xmm3[14],xmm14[14],xmm3[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm4, %xmm0 ; SSE2-NEXT: packuswb %xmm3, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $4, %xmm5 ; SSE2-NEXT: psllw $4, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm3, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm5 ; SSE2-NEXT: pandn %xmm5, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm7
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm7
; SSE2-NEXT: psllw $2, %xmm7 ; SSE2-NEXT: psllw $2, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm9, %xmm7 ; SSE2-NEXT: pand %xmm9, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
Show All 15 Lines
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm6, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm8, %xmm1 ; SSE2-NEXT: pand %xmm8, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1 ; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm1 ; SSE2-NEXT: pand %xmm13, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm6, %xmm2 ; SSE2-NEXT: packuswb %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pandn %xmm4, %xmm6
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm2 ; SSE2-NEXT: pand %xmm10, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm2
; SSE2-NEXT: pand %xmm11, %xmm2 ; SSE2-NEXT: pand %xmm11, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm2 ; SSE2-NEXT: pand %xmm13, %xmm2
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: movdqa %xmm15, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm15[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1],xmm3[2],xmm14[2],xmm3[3],xmm14[3],xmm3[4],xmm14[4],xmm3[5],xmm14[5],xmm3[6],xmm14[6],xmm3[7],xmm14[7] ; SSE2-NEXT: packuswb %xmm4, %xmm6
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7] ; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: packuswb %xmm6, %xmm3 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm8, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psrlw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm3 ; SSE2-NEXT: pandn %xmm4, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3
; SSE2-NEXT: por %xmm6, %xmm3 ; SSE2-NEXT: por %xmm6, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: pand %xmm9, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: pand %xmm10, %xmm3 ; SSE2-NEXT: pand %xmm10, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm11, %xmm3 ; SSE2-NEXT: pand %xmm11, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3 ; SSE2-NEXT: por %xmm5, %xmm3
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%b = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %a) %b = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %a)
ret <16 x i32> %b ret <16 x i32> %b
} }
define <8 x i64> @test_bitreverse_v8i64(<8 x i64> %a) nounwind { define <8 x i64> @test_bitreverse_v8i64(<8 x i64> %a) nounwind {
; SSE2-LABEL: test_bitreverse_v8i64: ; SSE2-LABEL: test_bitreverse_v8i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm3, %xmm15
; SSE2-NEXT: pxor %xmm14, %xmm14 ; SSE2-NEXT: pxor %xmm14, %xmm14
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm14[8],xmm3[9],xmm14[9],xmm3[10],xmm14[10],xmm3[11],xmm14[11],xmm3[12],xmm14[12],xmm3[13],xmm14[13],xmm3[14],xmm14[14],xmm3[15],xmm14[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3],xmm0[4],xmm14[4],xmm0[5],xmm14[5],xmm0[6],xmm14[6],xmm0[7],xmm14[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm4, %xmm0 ; SSE2-NEXT: packuswb %xmm3, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $4, %xmm5 ; SSE2-NEXT: psllw $4, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; SSE2-NEXT: movdqa %xmm3, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm5 ; SSE2-NEXT: pandn %xmm5, %xmm7
; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm7 ; SSE2-NEXT: movdqa %xmm0, %xmm7
; SSE2-NEXT: pand %xmm5, %xmm7 ; SSE2-NEXT: pand %xmm5, %xmm7
; SSE2-NEXT: psllw $2, %xmm7 ; SSE2-NEXT: psllw $2, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; SSE2-NEXT: pand %xmm9, %xmm7 ; SSE2-NEXT: pand %xmm9, %xmm7
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204]
; SSE2-NEXT: pand %xmm10, %xmm0 ; SSE2-NEXT: pand %xmm10, %xmm0
Show All 17 Lines
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm6, %xmm1 ; SSE2-NEXT: packuswb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm8, %xmm1 ; SSE2-NEXT: pand %xmm8, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm1 ; SSE2-NEXT: pand %xmm10, %xmm1
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm11, %xmm1 ; SSE2-NEXT: pand %xmm11, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm1 ; SSE2-NEXT: pand %xmm13, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: por %xmm6, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[1],xmm14[1],xmm2[2],xmm14[2],xmm2[3],xmm14[3],xmm2[4],xmm14[4],xmm2[5],xmm14[5],xmm2[6],xmm14[6],xmm2[7],xmm14[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; SSE2-NEXT: packuswb %xmm6, %xmm2 ; SSE2-NEXT: packuswb %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pandn %xmm4, %xmm6
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm4
; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: psllw $2, %xmm4
; SSE2-NEXT: pand %xmm9, %xmm6 ; SSE2-NEXT: pand %xmm9, %xmm4
; SSE2-NEXT: pand %xmm10, %xmm2 ; SSE2-NEXT: pand %xmm10, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm2
; SSE2-NEXT: pand %xmm11, %xmm2 ; SSE2-NEXT: pand %xmm11, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pand %xmm7, %xmm6 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: psrlw $1, %xmm6 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm12, %xmm6 ; SSE2-NEXT: pand %xmm12, %xmm4
; SSE2-NEXT: pand %xmm13, %xmm2 ; SSE2-NEXT: pand %xmm13, %xmm2
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: movdqa %xmm15, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm14[8],xmm6[9],xmm14[9],xmm6[10],xmm14[10],xmm6[11],xmm14[11],xmm6[12],xmm14[12],xmm6[13],xmm14[13],xmm6[14],xmm14[14],xmm6[15],xmm14[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm14[8],xmm4[9],xmm14[9],xmm4[10],xmm14[10],xmm4[11],xmm14[11],xmm4[12],xmm14[12],xmm4[13],xmm14[13],xmm4[14],xmm14[14],xmm4[15],xmm14[15]
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm15[2,3,0,1]
; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[3,2,1,0,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4] ; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,7,6,5,4]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1],xmm3[2],xmm14[2],xmm3[3],xmm14[3],xmm3[4],xmm14[4],xmm3[5],xmm14[5],xmm3[6],xmm14[6],xmm3[7],xmm14[7] ; SSE2-NEXT: packuswb %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1] ; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[3,2,1,0,4,5,6,7] ; SSE2-NEXT: pand %xmm3, %xmm4
; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4] ; SSE2-NEXT: psllw $4, %xmm4
; SSE2-NEXT: packuswb %xmm6, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pand %xmm8, %xmm6 ; SSE2-NEXT: pand %xmm8, %xmm6
; SSE2-NEXT: psllw $4, %xmm6 ; SSE2-NEXT: psrlw $4, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm6 ; SSE2-NEXT: pand %xmm3, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm3 ; SSE2-NEXT: pandn %xmm4, %xmm3
; SSE2-NEXT: psrlw $4, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3
; SSE2-NEXT: por %xmm6, %xmm3 ; SSE2-NEXT: por %xmm6, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm5 ; SSE2-NEXT: pand %xmm3, %xmm5
; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: psllw $2, %xmm5
; SSE2-NEXT: pand %xmm9, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm5
; SSE2-NEXT: pand %xmm10, %xmm3 ; SSE2-NEXT: pand %xmm10, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm11, %xmm3 ; SSE2-NEXT: pand %xmm11, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3 ; SSE2-NEXT: por %xmm5, %xmm3
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-fshl-256.ll

Show First 20 Lines • Show All 2,550 Lines • ▼ Show 20 Lines
; XOPAVX1-NEXT: vpshlb %xmm3, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpshlb %xmm3, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; XOPAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatconstant_funnnel_v32i8: ; XOPAVX2-LABEL: splatconstant_funnnel_v32i8:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1 ; XOPAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1
; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vpsllw $4, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsllw $4, %ymm0, %ymm0
; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: vpcmov {{.*}}(%rip), %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <32 x i8> %res ret <32 x i8> %res
} }

llvm/trunk/test/CodeGen/X86/vector-fshl-512.ll

Show First 20 Lines • Show All 1,498 Lines • ▼ Show 20 Lines; AVX512VLVBMI2-NEXT: retq
%res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>) %res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; AVX512F-LABEL: splatconstant_funnnel_v64i8: ; AVX512F-LABEL: splatconstant_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm3, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm3, %ymm2
; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_funnnel_v64i8: ; AVX512VL-LABEL: splatconstant_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm3, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm3, %ymm2
; AVX512VL-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_funnnel_v64i8: ; AVX512BW-LABEL: splatconstant_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm1, %zmm1 ; AVX512BW-NEXT: vpsrlw $4, %zmm1, %zmm1
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0
Show All 33 Lines

llvm/trunk/test/CodeGen/X86/vector-fshl-rot-256.ll

Show First 20 Lines • Show All 335 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %amt) nounwind { define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %amt) nounwind {
; AVX1-LABEL: var_funnnel_v32i8: ; AVX1-LABEL: var_funnnel_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5 ; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5
; AVX1-NEXT: vmovdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm5, %xmm5
; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5 ; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm10 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
; AVX1-NEXT: vpand %xmm10, %xmm3, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm2, %xmm4
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpsllw $2, %xmm2, %xmm7
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm4 ; AVX1-NEXT: vpand %xmm6, %xmm7, %xmm7
; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm7 ; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm7
; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm10, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4
; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4 ; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_funnnel_v32i8: ; AVX2-LABEL: var_funnnel_v32i8:
▲ Show 20 Lines • Show All 1,077 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind { define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8: ; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatconstant_funnnel_v32i8: ; AVX2-LABEL: splatconstant_funnnel_v32i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
Show All 32 Lines

llvm/trunk/test/CodeGen/X86/vector-fshl-rot-512.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> %amt) %res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> %amt)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind { define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
; AVX512F-LABEL: var_funnnel_v64i8: ; AVX512F-LABEL: var_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512F-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512F-NEXT: vpand %ymm8, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm7, %ymm4
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm9 ; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm8
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm10 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512F-NEXT: vpand %ymm7, %ymm8, %ymm8
; AVX512F-NEXT: vpand %ymm10, %ymm9, %ymm9 ; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512F-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm8, %ymm4, %ymm4
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm11 ; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm9
; AVX512F-NEXT: vpor %ymm4, %ymm11, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3 ; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm7, %ymm2
; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm10, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm9, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm8, %ymm2, %ymm2
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: var_funnnel_v64i8: ; AVX512VL-LABEL: var_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512VL-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2 ; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512VL-NEXT: vpand %ymm8, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm7, %ymm4
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm9 ; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm8
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm10 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512VL-NEXT: vpand %ymm7, %ymm8, %ymm8
; AVX512VL-NEXT: vpand %ymm10, %ymm9, %ymm9 ; AVX512VL-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512VL-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512VL-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm8, %ymm4, %ymm4
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm11 ; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm9
; AVX512VL-NEXT: vpor %ymm4, %ymm11, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3 ; AVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm7, %ymm2
; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm10, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm9, %ymm2, %ymm2 ; AVX512VL-NEXT: vpand %ymm8, %ymm2, %ymm2
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: var_funnnel_v64i8: ; AVX512BW-LABEL: var_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
▲ Show 20 Lines • Show All 554 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>) %res = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x) nounwind { define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x) nounwind {
; AVX512F-LABEL: splatconstant_funnnel_v64i8: ; AVX512F-LABEL: splatconstant_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_funnnel_v64i8: ; AVX512VL-LABEL: splatconstant_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_funnnel_v64i8: ; AVX512BW-LABEL: splatconstant_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0
Show All 15 Lines

llvm/trunk/test/CodeGen/X86/vector-fshr-256.ll

Show First 20 Lines • Show All 2,563 Lines • ▼ Show 20 Lines
; XOPAVX1-NEXT: vpshlb %xmm3, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpshlb %xmm3, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; XOPAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; XOPAVX1-NEXT: retq ; XOPAVX1-NEXT: retq
; ;
; XOPAVX2-LABEL: splatconstant_funnnel_v32i8: ; XOPAVX2-LABEL: splatconstant_funnnel_v32i8:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1 ; XOPAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1
; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
; XOPAVX2-NEXT: vpsllw $4, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpsllw $4, %ymm0, %ymm0
; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; XOPAVX2-NEXT: vpcmov {{.*}}(%rip), %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <32 x i8> %res ret <32 x i8> %res
} }

llvm/trunk/test/CodeGen/X86/vector-fshr-512.ll

Show First 20 Lines • Show All 1,490 Lines • ▼ Show 20 Lines; AVX512VLVBMI2-NEXT: retq
%res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>) %res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %y, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; AVX512F-LABEL: splatconstant_funnnel_v64i8: ; AVX512F-LABEL: splatconstant_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm3, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm3, %ymm2
; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_funnnel_v64i8: ; AVX512VL-LABEL: splatconstant_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm5, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm3, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm3, %ymm2
; AVX512VL-NEXT: vpand %ymm4, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_funnnel_v64i8: ; AVX512BW-LABEL: splatconstant_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm1, %zmm1 ; AVX512BW-NEXT: vpsrlw $4, %zmm1, %zmm1
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0
Show All 33 Lines

llvm/trunk/test/CodeGen/X86/vector-fshr-rot-256.ll

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %amt) nounwind { define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %amt) nounwind {
; AVX1-LABEL: var_funnnel_v32i8: ; AVX1-LABEL: var_funnnel_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5 ; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5
; AVX1-NEXT: vmovdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm5, %xmm5
; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vpxor %xmm10, %xmm10, %xmm10 ; AVX1-NEXT: vpxor %xmm8, %xmm8, %xmm8
; AVX1-NEXT: vpsubb %xmm5, %xmm10, %xmm5 ; AVX1-NEXT: vpsubb %xmm5, %xmm8, %xmm5
; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5 ; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm11 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
; AVX1-NEXT: vpand %xmm11, %xmm3, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm2, %xmm6
; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX1-NEXT: vpandn %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm2, %xmm6
; AVX1-NEXT: vpand %xmm7, %xmm6, %xmm6 ; AVX1-NEXT: vpand %xmm7, %xmm6, %xmm6
; AVX1-NEXT: vpor %xmm3, %xmm6, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5 ; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm9, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm4 ; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm6
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm4 ; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsubb %xmm1, %xmm10, %xmm1 ; AVX1-NEXT: vpsubb %xmm1, %xmm8, %xmm1
; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm11, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4
; AVX1-NEXT: vpand %xmm7, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm7, %xmm4, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm9, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4 ; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_funnnel_v32i8: ; AVX2-LABEL: var_funnnel_v32i8:
▲ Show 20 Lines • Show All 1,120 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind { define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8: ; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatconstant_funnnel_v32i8: ; AVX2-LABEL: splatconstant_funnnel_v32i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
Show All 32 Lines

llvm/trunk/test/CodeGen/X86/vector-fshr-rot-512.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> %amt) %res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> %amt)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind { define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
; AVX512F-LABEL: var_funnnel_v64i8: ; AVX512F-LABEL: var_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512F-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 ; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 ; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX512F-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm7, %ymm2, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm9 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512F-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm8, %ymm4
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm10 ; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm9
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm11 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512F-NEXT: vpand %ymm8, %ymm9, %ymm9
; AVX512F-NEXT: vpand %ymm11, %ymm10, %ymm10 ; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512F-NEXT: vpor %ymm4, %ymm10, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm10 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512F-NEXT: vpand %ymm10, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm9, %ymm4, %ymm4
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm12 ; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm10
; AVX512F-NEXT: vpor %ymm4, %ymm12, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm10, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsubb %ymm3, %ymm6, %ymm3 ; AVX512F-NEXT: vpsubb %ymm3, %ymm6, %ymm3
; AVX512F-NEXT: vpand %ymm8, %ymm3, %ymm3 ; AVX512F-NEXT: vpand %ymm7, %ymm3, %ymm3
; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm9, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm8, %ymm2
; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm11, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm8, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm10, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm9, %ymm2, %ymm2
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: var_funnnel_v64i8: ; AVX512VL-LABEL: var_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512VL-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6 ; AVX512VL-NEXT: vpxor %xmm6, %xmm6, %xmm6
; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2 ; AVX512VL-NEXT: vpsubb %ymm2, %ymm6, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX512VL-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512VL-NEXT: vpand %ymm7, %ymm2, %ymm2
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm9 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512VL-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm8, %ymm4
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm10 ; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm9
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm11 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512VL-NEXT: vpand %ymm8, %ymm9, %ymm9
; AVX512VL-NEXT: vpand %ymm11, %ymm10, %ymm10 ; AVX512VL-NEXT: vpor %ymm4, %ymm9, %ymm4
; AVX512VL-NEXT: vpor %ymm4, %ymm10, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm10 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512VL-NEXT: vpand %ymm10, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm9, %ymm4, %ymm4
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm12 ; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm10
; AVX512VL-NEXT: vpor %ymm4, %ymm12, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm10, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsubb %ymm3, %ymm6, %ymm3 ; AVX512VL-NEXT: vpsubb %ymm3, %ymm6, %ymm3
; AVX512VL-NEXT: vpand %ymm8, %ymm3, %ymm3 ; AVX512VL-NEXT: vpand %ymm7, %ymm3, %ymm3
; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm9, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm8, %ymm2
; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm11, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm8, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm10, %ymm2, %ymm2 ; AVX512VL-NEXT: vpand %ymm9, %ymm2, %ymm2
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: var_funnnel_v64i8: ; AVX512BW-LABEL: var_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
▲ Show 20 Lines • Show All 562 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>) %res = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %x, <32 x i16> %x, <32 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>)
ret <32 x i16> %res ret <32 x i16> %res
} }
define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x) nounwind { define <64 x i8> @splatconstant_funnnel_v64i8(<64 x i8> %x) nounwind {
; AVX512F-LABEL: splatconstant_funnnel_v64i8: ; AVX512F-LABEL: splatconstant_funnnel_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_funnnel_v64i8: ; AVX512VL-LABEL: splatconstant_funnnel_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_funnnel_v64i8: ; AVX512BW-LABEL: splatconstant_funnnel_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm0
Show All 15 Lines

llvm/trunk/test/CodeGen/X86/vector-rotate-256.ll

Show First 20 Lines • Show All 331 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %or ret <16 x i16> %or
} }
define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { define <32 x i8> @var_rotate_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; AVX1-LABEL: var_rotate_v32i8: ; AVX1-LABEL: var_rotate_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5 ; AVX1-NEXT: vpsllw $4, %xmm2, %xmm5
; AVX1-NEXT: vmovdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm5, %xmm5
; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5 ; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm10 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
; AVX1-NEXT: vpand %xmm10, %xmm3, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm2, %xmm4
; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpsllw $2, %xmm2, %xmm7
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm4 ; AVX1-NEXT: vpand %xmm6, %xmm7, %xmm7
; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm7 ; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm7
; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm7, %xmm3
; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm5
; AVX1-NEXT: vpand %xmm9, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $6, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm10, %xmm3, %xmm3 ; AVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4 ; AVX1-NEXT: vpsllw $2, %xmm0, %xmm4
; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3 ; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 ; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4 ; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 ; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_rotate_v32i8: ; AVX2-LABEL: var_rotate_v32i8:
▲ Show 20 Lines • Show All 1,082 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %or ret <16 x i16> %or
} }
define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind { define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind {
; AVX1-LABEL: splatconstant_rotate_v32i8: ; AVX1-LABEL: splatconstant_rotate_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatconstant_rotate_v32i8: ; AVX2-LABEL: splatconstant_rotate_v32i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vpand {{.*}}(%rip), %ymm1, %ymm1
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines; XOPAVX2-NEXT: retq
ret <16 x i16> %or ret <16 x i16> %or
} }
define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind { define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind {
; AVX1-LABEL: splatconstant_rotate_mask_v32i8: ; AVX1-LABEL: splatconstant_rotate_mask_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: splatconstant_rotate_mask_v32i8: ; AVX2-LABEL: splatconstant_rotate_mask_v32i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1 ; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-rotate-512.ll

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%or = or <32 x i16> %shl, %lshr %or = or <32 x i16> %shl, %lshr
ret <32 x i16> %or ret <32 x i16> %or
} }
define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { define <64 x i8> @var_rotate_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; AVX512F-LABEL: var_rotate_v64i8: ; AVX512F-LABEL: var_rotate_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512F-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512F-NEXT: vpand %ymm6, %ymm4, %ymm4 ; AVX512F-NEXT: vpandn %ymm4, %ymm6, %ymm4
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm8 ; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm7
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512F-NEXT: vpand %ymm6, %ymm7, %ymm7
; AVX512F-NEXT: vpand %ymm9, %ymm8, %ymm8 ; AVX512F-NEXT: vpor %ymm4, %ymm7, %ymm4
; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512F-NEXT: vpand %ymm8, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm10 ; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm8
; AVX512F-NEXT: vpor %ymm4, %ymm10, %ymm4 ; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512F-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm6, %ymm2
; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512F-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512F-NEXT: vpand %ymm6, %ymm4, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512F-NEXT: vpand %ymm7, %ymm2, %ymm2
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512F-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: var_rotate_v64i8: ; AVX512VL-LABEL: var_rotate_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm5, %ymm4
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm6
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm5, %ymm6, %ymm6
; AVX512VL-NEXT: vpand %ymm7, %ymm6, %ymm6
; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
; AVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4 ; AVX512VL-NEXT: vpandn %ymm4, %ymm6, %ymm4
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm8 ; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm7
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] ; AVX512VL-NEXT: vpand %ymm6, %ymm7, %ymm7
; AVX512VL-NEXT: vpand %ymm9, %ymm8, %ymm8 ; AVX512VL-NEXT: vpor %ymm4, %ymm7, %ymm4
; AVX512VL-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4 ; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm4
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
; AVX512VL-NEXT: vpand %ymm8, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm10 ; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm8
; AVX512VL-NEXT: vpor %ymm4, %ymm10, %ymm4 ; AVX512VL-NEXT: vpor %ymm4, %ymm8, %ymm4
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm5, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm5, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3 ; AVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $6, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm6, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm6, %ymm2
; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4 ; AVX512VL-NEXT: vpsllw $2, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm9, %ymm4, %ymm4 ; AVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm8, %ymm2, %ymm2 ; AVX512VL-NEXT: vpand %ymm7, %ymm2, %ymm2
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4 ; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2 ; AVX512VL-NEXT: vpor %ymm2, %ymm4, %ymm2
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3 ; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: var_rotate_v64i8: ; AVX512BW-LABEL: var_rotate_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
▲ Show 20 Lines • Show All 553 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%or = or <32 x i16> %shl, %lshr %or = or <32 x i16> %shl, %lshr
ret <32 x i16> %or ret <32 x i16> %or
} }
define <64 x i8> @splatconstant_rotate_v64i8(<64 x i8> %a) nounwind { define <64 x i8> @splatconstant_rotate_v64i8(<64 x i8> %a) nounwind {
; AVX512F-LABEL: splatconstant_rotate_v64i8: ; AVX512F-LABEL: splatconstant_rotate_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_rotate_v64i8: ; AVX512VL-LABEL: splatconstant_rotate_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm2
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_rotate_v64i8: ; AVX512BW-LABEL: splatconstant_rotate_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
%or = or <32 x i16> %lmask, %rmask %or = or <32 x i16> %lmask, %rmask
ret <32 x i16> %or ret <32 x i16> %or
} }
define <64 x i8> @splatconstant_rotate_mask_v64i8(<64 x i8> %a) nounwind { define <64 x i8> @splatconstant_rotate_mask_v64i8(<64 x i8> %a) nounwind {
; AVX512F-LABEL: splatconstant_rotate_mask_v64i8: ; AVX512F-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512F-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512F-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39] ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39]
; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm5 ; AVX512F-NEXT: vpsrlw $4, %ymm1, %ymm4
; AVX512F-NEXT: vpand %ymm3, %ymm5, %ymm3 ; AVX512F-NEXT: vpandn %ymm4, %ymm3, %ymm4
; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512F-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpor %ymm3, %ymm1, %ymm1 ; AVX512F-NEXT: vpor %ymm4, %ymm1, %ymm1
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: splatconstant_rotate_mask_v64i8: ; AVX512VL-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2 ; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
; AVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2 ; AVX512VL-NEXT: vpandn %ymm2, %ymm3, %ymm2
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] ; AVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm0
; AVX512VL-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39]
; AVX512VL-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm5 ; AVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm4
; AVX512VL-NEXT: vpand %ymm3, %ymm5, %ymm3 ; AVX512VL-NEXT: vpandn %ymm4, %ymm3, %ymm4
; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpsllw $4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX512VL-NEXT: vpor %ymm3, %ymm1, %ymm1 ; AVX512VL-NEXT: vpor %ymm4, %ymm1, %ymm1
; AVX512VL-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: splatconstant_rotate_mask_v64i8: ; AVX512BW-LABEL: splatconstant_rotate_mask_v64i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1 ; AVX512BW-NEXT: vpsllw $4, %zmm0, %zmm1
; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm0
; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
Show All 19 Lines