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Differential D55805

AMDGPU/GlobalISel: RegBankSelect for amdgcn.wqm.vote
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Authored by arsenm on Dec 17 2018, 8:36 PM.

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tstellar

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Event Timeline

arsenm created this revision.Dec 17 2018, 8:36 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 17 2018, 8:36 PM
tstellar accepted this revision.Dec 19 2018, 1:57 PM

LGTM.

This revision is now accepted and ready to land.Dec 19 2018, 1:57 PM
arsenm closed this revision.Dec 20 2018, 7:24 PM

r349882

Revision Contents

PathSize
lib/
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
56 lines

Diff 178587

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 619 Lines • ▼ Show 20 Lines case AMDGPU::G_INTRINSIC: {
case Intrinsic::minnum: case Intrinsic::minnum:
case Intrinsic::amdgcn_cvt_pkrtz: case Intrinsic::amdgcn_cvt_pkrtz:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
case Intrinsic::amdgcn_kernarg_segment_ptr: { case Intrinsic::amdgcn_kernarg_segment_ptr: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break; break;
} }
case Intrinsic::amdgcn_wqm_vote: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = OpdsMapping[2]
= AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break;
}
} }
break; break;
} }
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: { case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
switch (MI.getOperand(0).getIntrinsicID()) { switch (MI.getOperand(0).getIntrinsicID()) {
default: default:
return getInvalidInstructionMapping(); return getInvalidInstructionMapping();
case Intrinsic::amdgcn_exp_compr: case Intrinsic::amdgcn_exp_compr:
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-wqm-vote.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: wqm_vote_scc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: wqm_vote_scc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
...
---
name: wqm_vote_vcc
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: wqm_vote_vcc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[ICMP]](s1)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
...
---
name: wqm_vote_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: wqm_vote_sgpr
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[INT:%[0-9]+]]:sgpr(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[TRUNC]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %1
...