This is an archive of the discontinued LLVM Phabricator instance.

[X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS.
ClosedPublic

Authored by craig.topper on Dec 1 2018, 12:07 PM.

Details

Summary

We need to unpackl and unpackh the operands to use two vXi16 multiplies. Previously it looks like the low unpack would get constant folded at least in the 128-bit case after shuffle lowering turned the unpackl into ZERO_EXTEND_VECTOR_INREG and X86 custom DAG combined it. The same doesn't happen for the high half. So we'd load a constant and then shuffle it. But the low half would just be loaded and used by the multiply directly.

After this patch we now end up with a constant pool entry for the low and high unpacks separately with no shuffle operations.

This is a step towards removing custom constant folding for ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG in the X86 backend.

Diff Detail

Event Timeline

craig.topper created this revision.Dec 1 2018, 12:07 PM

Rebase and do the same in LowerMULH

craig.topper retitled this revision from [X86] Teach LowerMUL for vXi8 to unpack constant RHS. to [X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS..Dec 1 2018, 2:15 PM
craig.topper edited the summary of this revision. (Show Details)

Fix a comment

RKSimon accepted this revision.Dec 3 2018, 12:18 AM

LGTM

This revision is now accepted and ready to land.Dec 3 2018, 12:18 AM
This revision was automatically updated to reflect the committed changes.