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Differential D54790

[ARM] Prevent parallel macs for unsigned values
ClosedPublic

Authored by samparker on Nov 21 2018, 5:20 AM.

Details

Reviewers
SjoerdMeijer
Commits
rG5338f7aae42f: [ARM] Prevent parallel macs for unsigned values
rL347542: [ARM] Prevent parallel macs for unsigned values
Summary

Both zext and sext are currently allowed during the search for narrow sequences and sexts operands are later added to the mac candidates. But operands of muls are also added, without checking whether they're sext or zext, which means we can generate a signed smlad when we shouldn't.

Diff Detail

Repository
rL LLVM

Event Timeline

samparker created this revision.Nov 21 2018, 5:20 AM
Herald added subscribers: chrib, kristof.beyls, javed.absar. · View Herald TranscriptNov 21 2018, 5:21 AM
SjoerdMeijer accepted this revision.Nov 23 2018, 2:05 AM

LGTM

This revision is now accepted and ready to land.Nov 23 2018, 2:05 AM
Closed by commit rL347542: [ARM] Prevent parallel macs for unsigned values (authored by sam_parker). · Explain WhyNov 26 2018, 2:25 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
20 lines
test/
CodeGen/
ARM/
80 lines
41 lines
86 lines

Diff 175214

llvm/trunk/lib/Target/ARM/ARMParallelDSP.cpp

Show First 20 Lines • Show All 519 Lines • ▼ Show 20 Linesstatic void MatchParallelMACSequences(Reduction &R,
// Returns false to signal the search should be stopped. // Returns false to signal the search should be stopped.
std::function<bool(Value*)> Match = std::function<bool(Value*)> Match =
[&Candidates, &Match](Value *V) -> bool { [&Candidates, &Match](Value *V) -> bool {
auto *I = dyn_cast<Instruction>(V); auto *I = dyn_cast<Instruction>(V);
if (!I) if (!I)
return false; return false;
Value *MulOp0, *MulOp1;
switch (I->getOpcode()) { switch (I->getOpcode()) {
case Instruction::Add: case Instruction::Add:
if (Match(I->getOperand(0)) || (Match(I->getOperand(1)))) if (Match(I->getOperand(0)) || (Match(I->getOperand(1))))
return true; return true;
break; break;
case Instruction::Mul: case Instruction::Mul: {
if (match (I, (m_Mul(m_Value(MulOp0), m_Value(MulOp1))))) { Value *MulOp0 = I->getOperand(0);
Value *MulOp1 = I->getOperand(1);
if (isa<SExtInst>(MulOp0) && isa<SExtInst>(MulOp1))
AddMACCandidate(Candidates, I, MulOp0, MulOp1); AddMACCandidate(Candidates, I, MulOp0, MulOp1);
return false; return false;
} }
break;
case Instruction::SExt: case Instruction::SExt:
if (match (I, (m_SExt(m_Mul(m_Value(MulOp0), m_Value(MulOp1)))))) { return Match(I->getOperand(0));
Instruction *Mul = cast<Instruction>(I->getOperand(0));
AddMACCandidate(Candidates, Mul, MulOp0, MulOp1);
return false;
}
break;
} }
return false; return false;
}; };
while (Match (Acc)); while (Match (Acc));
LLVM_DEBUG(dbgs() << "Finished matching MAC sequences, found " LLVM_DEBUG(dbgs() << "Finished matching MAC sequences, found "
<< Candidates.size() << " candidates.\n"); << Candidates.size() << " candidates.\n");
} }
▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/ARM/smlad0.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines; And two reduction statements here:
%conv25 = sext i16 %3 to i32 %conv25 = sext i16 %3 to i32
%mul26 = mul nsw i32 %conv24, %conv25 %mul26 = mul nsw i32 %conv24, %conv25
%add27 = add i32 %mul21, %mac2.057 %add27 = add i32 %mul21, %mac2.057
%add28 = add i32 %add27, %mul26 %add28 = add i32 %add27, %mul26
%add29 = add nuw nsw i32 %i.056, 4 %add29 = add nuw nsw i32 %i.056, 4
%cmp = icmp slt i32 %add29, %arg %cmp = icmp slt i32 %add29, %arg
br i1 %cmp, label %for.body, label %for.cond.cleanup br i1 %cmp, label %for.body, label %for.cond.cleanup
} }
define i32 @one_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @one_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
define i32 @two_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @two_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
ret i32 %mac1.0.lcssa
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%add10 = add i32 %mul, %mac1.026
%add11 = add i32 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}

llvm/trunk/test/CodeGen/ARM/smlald0.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines; And two reduction statements here:
%conv25 = sext i16 %3 to i64 %conv25 = sext i16 %3 to i64
%mul26 = mul nsw i64 %conv24, %conv25 %mul26 = mul nsw i64 %conv24, %conv25
%add27 = add i64 %mul21, %mac2.057 %add27 = add i64 %mul21, %mac2.057
%add28 = add i64 %add27, %mul26 %add28 = add i64 %add27, %mul26
%add29 = add nuw nsw i32 %i.056, 4 %add29 = add nuw nsw i32 %i.056, 4
%cmp = icmp slt i32 %add29, %arg %cmp = icmp slt i32 %add29, %arg
br i1 %cmp, label %for.body, label %for.cond.cleanup br i1 %cmp, label %for.body, label %for.cond.cleanup
} }
define i64 @reduction_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @reduction_zext
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i64 [ 0, %entry ], [ %add11, %for.body ]
ret i64 %mac1.0.lcssa
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = sext i16 %2 to i64
%conv4 = zext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv4
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = sext i16 %3 to i64
%conv8 = zext i16 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
%add10 = add i64 %mul, %mac1.026
%add11 = add i64 %mul9, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}

llvm/trunk/test/CodeGen/ARM/smlald2.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines; And two reduction statements here:
%mul26 = mul nsw i32 %conv24, %conv25 %mul26 = mul nsw i32 %conv24, %conv25
%sext3 = sext i32 %mul26 to i64 %sext3 = sext i32 %mul26 to i64
%add27 = add i64 %sext2, %mac2.057 %add27 = add i64 %sext2, %mac2.057
%add28 = add i64 %add27, %sext3 %add28 = add i64 %add27, %sext3
%add29 = add nuw nsw i32 %i.056, 4 %add29 = add nuw nsw i32 %i.056, 4
%cmp = icmp slt i32 %add29, %arg %cmp = icmp slt i32 %add29, %arg
br i1 %cmp, label %for.body, label %for.cond.cleanup br i1 %cmp, label %for.body, label %for.cond.cleanup
} }
define i64 @zext_mul_reduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @zext_mul_reduction
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i64 [ 0, %entry ], [ %add11, %for.body ]
ret i64 %mac1.0.lcssa
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%sext0 = sext i32 %mul to i64
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%sext1 = sext i32 %mul9 to i64
%add10 = add i64 %sext0, %mac1.026
%add11 = add i64 %sext1, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
define i64 @zext_add_reduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
; CHECK-LABEL: @zext_add_reduction
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
%.pre = load i16, i16* %arg3, align 2
%.pre27 = load i16, i16* %arg2, align 2
br label %for.body
for.cond.cleanup:
%mac1.0.lcssa = phi i64 [ 0, %entry ], [ %add11, %for.body ]
ret i64 %mac1.0.lcssa
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
%0 = load i16, i16* %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
%arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
%1 = load i16, i16* %arrayidx1, align 2
%arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
%2 = load i16, i16* %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%sext0 = zext i32 %mul to i64
%arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
%3 = load i16, i16* %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
%sext1 = zext i32 %mul9 to i64
%add10 = add i64 %sext0, %mac1.026
%add11 = add i64 %sext1, %add10
%exitcond = icmp ne i32 %add, %arg
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}