[x86] try to lower multiply i8 with constant to LEA

[spatel]

Summary

This is an attempt to avoid regressions seen when D54640 is extended to include add ops, so it's another patch towards solving PR32023:
https://bugs.llvm.org/show_bug.cgi?id=32023

LEA formation is scattered between combines, DAG-to-DAG, and machine passes like "Two-Address instruction pass", so I'm not sure if this is the best solution.

The idea here is to rely on the existing DAG-to-DAG logic for 32-bit LEA formation; no edits needed in there. If this is the right approach, then I'd extend this to handle more constants; 3/5/9 are just the most obvious winners for size/speed regardless of uarch. GCC forms LEA for 8-bit mul much more aggressively.

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

23430

Why ZERO_EXTEND and not ANY_EXTEND?

[spatel]

lib/Target/X86/X86ISelLowering.cpp

23430

No reason. I just didn't think of it. I'll change it if we're proceeding here, or better to just push ahead with D54803?

[spatel]

Abandoning in favor of D54803.

lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   // Integer absolute.
   if (Subtarget.hasCMov()) {
     setOperationAction(ISD::ABS            , MVT::i16  , Custom);
     setOperationAction(ISD::ABS            , MVT::i32  , Custom);
     if (Subtarget.is64Bit())
       setOperationAction(ISD::ABS          , MVT::i64  , Custom);
   }
 
+  // 8-bit shl/multiply might be better off as LEA depending on the operands.
+  setOperationAction(ISD::MUL, MVT::i8, Custom);
+
   // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
   // operation.
   setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
   setOperationAction(ISD::UINT_TO_FP       , MVT::i8   , Promote);
   setOperationAction(ISD::UINT_TO_FP       , MVT::i16  , Promote);
 
   if (Subtarget.is64Bit()) {
     if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
   SDValue Cond = DAG.getSetCC(DL, VT, N0, N1, CC);
   return DAG.getSelect(DL, VT, Cond, N0, N1);
 }
 
 static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
                         SelectionDAG &DAG) {
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
-
   if (VT.getScalarType() == MVT::i1)
     return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
 
   // Decompose 256-bit ops into 128-bit ops.
   if (VT.is256BitVector() && !Subtarget.hasInt256())
     return split256IntArith(Op, DAG);
 
   SDValue A = Op.getOperand(0);
   SDValue B = Op.getOperand(1);
+  if (VT == MVT::i8) {
+    if (isa<ConstantSDNode>(B)) {
+      uint64_t MulC = Op.getConstantOperandVal(1);
+      if (MulC == 3 || MulC == 5 || MulC == 9) {
+        // Extend/truncate an 8-bit multiply to 32-bit to allow LEA formation.
+        SDValue ZextOp0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, A);
+        SDValue NewMul = DAG.getNode(ISD::MUL, dl, MVT::i32, ZextOp0,
+                                     DAG.getConstant(MulC, dl, MVT::i32));
+        return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, NewMul);
+      }
+    }
+    return Op;
+  }
 
   // Lower v16i8/v32i8/v64i8 mul as sign-extension to v8i16/v16i16/v32i16
   // vector pairs, multiply and truncate.
   if (VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) {
     int NumElts = VT.getVectorNumElements();
 
     if ((VT == MVT::v16i8 && Subtarget.hasInt256()) ||
         (VT == MVT::v32i8 && Subtarget.canExtendTo512BW())) {

test/CodeGen/X86/mul-constant-i8.ll

 ; X64-NEXT:    retq
   %m = mul i8 %x, 2
   ret i8 %m
 }
 
 define i8 @test_mul_by_3(i8 %x) {
 ; X64-LABEL: test_mul_by_3:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movb $3, %cl
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi,2), %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
-; X64-NEXT:    mulb %cl
 ; X64-NEXT:    retq
   %m = mul i8 %x, 3
   ret i8 %m
 }
 
 define i8 @test_mul_by_4(i8 %x) {
 ; X64-LABEL: test_mul_by_4:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    shlb $2, %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    retq
   %m = mul i8 %x, 4
   ret i8 %m
 }
 
 define i8 @test_mul_by_5(i8 %x) {
 ; X64-LABEL: test_mul_by_5:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movb $5, %cl
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi,4), %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
-; X64-NEXT:    mulb %cl
 ; X64-NEXT:    retq
   %m = mul i8 %x, 5
   ret i8 %m
 }
 
 define i8 @test_mul_by_6(i8 %x) {
 ; X64-LABEL: test_mul_by_6:
 ; X64:       # %bb.0:

 ; X64-NEXT:    retq
   %m = mul i8 %x, 8
   ret i8 %m
 }
 
 define i8 @test_mul_by_9(i8 %x) {
 ; X64-LABEL: test_mul_by_9:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movb $9, %cl
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi,8), %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
-; X64-NEXT:    mulb %cl
 ; X64-NEXT:    retq
   %m = mul i8 %x, 9
   ret i8 %m
 }
 
 define i8 @test_mul_by_10(i8 %x) {
 ; X64-LABEL: test_mul_by_10:
 ; X64:       # %bb.0: