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Implement computeKnownBits for scalar_to_vector
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Authored by rampitec on Nov 19 2018, 2:42 PM.

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LGTM

This revision is now accepted and ready to land.Nov 19 2018, 3:03 PM

This revision was automatically updated to reflect the committed changes.

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SelectionDAG/

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test/

CodeGen/

AMDGPU/

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Show First 20 Lines • Show All 2,339 Lines • ▼ Show 20 Lines	if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
uint64_t Idx = SubIdx->getZExtValue();		uint64_t Idx = SubIdx->getZExtValue();
APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);		APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
Known = computeKnownBits(Src, DemandedSrc, Depth + 1);		Known = computeKnownBits(Src, DemandedSrc, Depth + 1);
} else {		} else {
Known = computeKnownBits(Src, Depth + 1);		Known = computeKnownBits(Src, Depth + 1);
}		}
break;		break;
}		}
		case ISD::SCALAR_TO_VECTOR: {
		// We know about scalar_to_vector as much as we know about it source,
		// which becomes the first element of otherwise unknown vector.
		if (DemandedElts != 1)
		break;

		SDValue N0 = Op.getOperand(0);
		Known = computeKnownBits(N0, DemandedElts, Depth + 1);
		if (N0.getValueSizeInBits() != BitWidth)
		Known = Known.trunc(BitWidth);

		break;
		}
case ISD::BITCAST: {		case ISD::BITCAST: {
SDValue N0 = Op.getOperand(0);		SDValue N0 = Op.getOperand(0);
EVT SubVT = N0.getValueType();		EVT SubVT = N0.getValueType();
unsigned SubBitWidth = SubVT.getScalarSizeInBits();		unsigned SubBitWidth = SubVT.getScalarSizeInBits();

// Ignore bitcasts from unsupported types.		// Ignore bitcasts from unsupported types.
if (!(SubVT.isInteger() \|\| SubVT.isFloatingPoint()))		if (!(SubVT.isInteger() \|\| SubVT.isFloatingPoint()))
break;		break;
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	Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
	; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8:			; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8:
	; GCN: s_waitcnt			; GCN: s_waitcnt
	; GFX9-NEXT: flat_load_ubyte_d16 v2, v[0:1]			; GFX9-NEXT: flat_load_ubyte_d16 v2, v[0:1]
	; GFX9-NEXT: s_waitcnt			; GFX9-NEXT: s_waitcnt
	; GFX9-NEXT: global_store_dword v[0:1], v2			; GFX9-NEXT: global_store_dword v[0:1], v2
	; GFX9-NEXT: s_waitcnt			; GFX9-NEXT: s_waitcnt
	; GFX9-NEXT: s_setpc_b64			; GFX9-NEXT: s_setpc_b64

	; VI: flat_load_ubyte v{{[0-9]+}}			; VI: flat_load_ubyte [[LO:v[0-9]+]]
	; VI: v_or_b32_e32			; VI: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, v2
				; VI: s_mov_b32 [[MASK:s[0-9]+]], 0x5040c00
				; VI: v_perm_b32 [[RES:v[0-9]+]], [[HI]], [[LO]], [[MASK]]
				; VI: flat_store_dword v[0:1], [[RES]]
	define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {			define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
	entry:			entry:
	%reg.bc = bitcast i32 %reg to <2 x i16>			%reg.bc = bitcast i32 %reg to <2 x i16>
	%load = load i8, i8* %in			%load = load i8, i8* %in
	%ext = zext i8 %load to i16			%ext = zext i8 %load to i16
	%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0			%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
	store <2 x i16> %build1, <2 x i16> addrspace(1)* undef			store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
	ret void			ret void
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