[SelectionDAG] Teach getNode to constant fold SIGN/ZERO/ANY_EXTEND_VECTOR_INREG

[craig.topper]

Summary

getNode can constant fold vector ZERO/SIGN/ANY_EXTEND but not the VECTOR_INREG variants. This patch fixes that.

Some X86 specific constant folding on these nodes during DAG combine prevents seeing any changes in tests from this. I'm trying to work through some other issues to make the X86 specific constant folding unneeded.

[RKSimon]

Can any of the X86 constant folding code be removed ensure that this code is being used with existing tests?

[RKSimon]

Any movement on this?

[craig.topper]

This is probably going to be a lot harder to test after r346728.

[craig.topper]

Removing any of the constant folding code in X86 requires committing D54276 first so that we can still see constant MULH inputs as build_vectors and DAG combine them that way. With MULH lowering happening during DAG legalization we don't get a chance to constant fold until they have been turned into constant pool entries and that requires target specific constant folding.

[RKSimon]

In D54278#1303494, @craig.topper wrote:

Removing any of the constant folding code in X86 requires committing D54276 first so that we can still see constant MULH inputs as build_vectors and DAG combine them that way. With MULH lowering happening during DAG legalization we don't get a chance to constant fold until they have been turned into constant pool entries and that requires target specific constant folding.

D54276 landed - can the X86 folding now be removed as part of this?

[craig.topper]

I removed the custom combine in r348237. This patch doesn't provide any test changes. Probably due to a combination of the DAG combine for constant folding being enabled to run later, the MULH lowering being legalized earlier, and constant vectors being explicitly handled in the MUL/MULH lowering.

[craig.topper]

I'm happy to abandon this.

[RKSimon]

In D54278#1325013, @craig.topper wrote:

I'm happy to abandon this.

SGTM if neither DAG or X86-specific folds are necessary

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (BV->isConstant()) {
       case ISD::FFLOOR:
       case ISD::FP_EXTEND:
       case ISD::FP_TO_SINT:
       case ISD::FP_TO_UINT:
       case ISD::TRUNCATE:
       case ISD::ANY_EXTEND:
       case ISD::ZERO_EXTEND:
       case ISD::SIGN_EXTEND:
+      case ISD::ANY_EXTEND_VECTOR_INREG:
+      case ISD::ZERO_EXTEND_VECTOR_INREG:
+      case ISD::SIGN_EXTEND_VECTOR_INREG:
       case ISD::UINT_TO_FP:
       case ISD::SINT_TO_FP:
       case ISD::ABS:
       case ISD::BITREVERSE:
       case ISD::BSWAP:
       case ISD::CTLZ:
       case ISD::CTLZ_ZERO_UNDEF:
       case ISD::CTTZ:
SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode,
 
   if (isUndef(Opcode, Ops))
     return getUNDEF(VT);
 
   // We can only fold vectors - maybe merge with FoldConstantArithmetic someday?
   if (!VT.isVector())
     return SDValue();
 
+  // VECTOR_INREG opcodes allow more elements in source than dest.
+  bool InVecExtend = Opcode == ISD::ANY_EXTEND_VECTOR_INREG ||
+                     Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
+                     Opcode == ISD::SIGN_EXTEND_VECTOR_INREG;
+
   unsigned NumElts = VT.getVectorNumElements();
 
   auto IsScalarOrSameVectorSize = [&](const SDValue &Op) {
     return !Op.getValueType().isVector() ||
-           Op.getValueType().getVectorNumElements() == NumElts;
+           (!InVecExtend &&
+            Op.getValueType().getVectorNumElements() == NumElts) ||
+           (InVecExtend &&
+            Op.getValueType().getVectorNumElements() >= NumElts);
   };
 
   auto IsConstantBuildVectorOrUndef = [&](const SDValue &Op) {
     BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op);
     return (Op.isUndef()) || (Op.getOpcode() == ISD::CONDCODE) ||
            (BV && BV->isConstant());
   };
 
SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode,
   // ensure that its scalar size is at least as large as source.
   EVT LegalSVT = VT.getScalarType();
   if (NewNodesMustHaveLegalTypes && LegalSVT.isInteger()) {
     LegalSVT = TLI->getTypeToTransformTo(*getContext(), LegalSVT);
     if (LegalSVT.bitsLT(VT.getScalarType()))
       return SDValue();
   }
 
+  // Invec opcodes need to be changed to their scalar opcode.
+  switch (Opcode) {
+  case ISD::ANY_EXTEND_VECTOR_INREG:  Opcode = ISD::ANY_EXTEND; break;
+  case ISD::SIGN_EXTEND_VECTOR_INREG: Opcode = ISD::SIGN_EXTEND; break;
+  case ISD::ZERO_EXTEND_VECTOR_INREG: Opcode = ISD::ZERO_EXTEND; break;
+  }
+
   // Constant fold each scalar lane separately.
   SmallVector<SDValue, 4> ScalarResults;
   for (unsigned i = 0; i != NumElts; i++) {
     SmallVector<SDValue, 4> ScalarOps;
     for (SDValue Op : Ops) {
       EVT InSVT = Op.getValueType().getScalarType();
       BuildVectorSDNode *InBV = dyn_cast<BuildVectorSDNode>(Op);
       if (!InBV) {