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Differential D53901

[ARM][NFC] Make tests immune to better div optimizations
ClosedPublic

Authored by xbolva00 on Oct 30 2018, 2:54 PM.

Details

Reviewers
spatel
Commits
rGf739066e8a80: [ARM][NFC] Make tests immune to better div optimizations
rL345665: [ARM][NFC] Make tests immune to better div optimizations
Summary

Related to D52504

Diff Detail

Repository
rL LLVM

Event Timeline

xbolva00 created this revision.Oct 30 2018, 2:54 PM
Herald added subscribers: llvm-commits, chrib, kristof.beyls, javed.absar. · View Herald TranscriptOct 30 2018, 2:54 PM
xbolva00 updated this revision to Diff 171812.Oct 30 2018, 3:02 PM
spatel accepted this revision.Oct 30 2018, 3:03 PM

LGTM

This revision is now accepted and ready to land.Oct 30 2018, 3:03 PM
Closed by commit rL345665: [ARM][NFC] Make tests immune to better div optimizations (authored by xbolva00). · Explain WhyOct 30 2018, 3:10 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
ARM/
17 lines
13 lines
4 lines

Diff 171818

llvm/trunk/test/CodeGen/ARM/fold-sext-sextload.ll

; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s ; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
define <4 x i8> @i(<4 x i8>*) !dbg !8 { define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
%2 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14 %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0) ; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0)
; CHECK-NEXT: VMOVLsv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14 ; CHECK: VMOVLsv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
; CHECK-NEXT: VMOVLsv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14 ; CHECK: VMOVLsv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
%4 = sdiv <4 x i8> %1, %3, !dbg !15
%3 = sdiv <4 x i8> zeroinitializer, %2, !dbg !15 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !11, metadata !DIExpression()), !dbg !14
call void @llvm.dbg.value(metadata <4 x i8> %2, metadata !11, metadata !DIExpression()), !dbg !14 call void @llvm.dbg.value(metadata <4 x i8> %4, metadata !13, metadata !DIExpression()), !dbg !15
call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !13, metadata !DIExpression()), !dbg !15 ret <4 x i8> %4, !dbg !16
ret <4 x i8> %3, !dbg !16
} }
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.debugify = !{!0, !1, !2, !3} !llvm.debugify = !{!0, !1, !2, !3}
!llvm.module.flags = !{!4} !llvm.module.flags = !{!4}
!llvm.dbg.cu = !{!5} !llvm.dbg.cu = !{!5}
Show All 18 Lines

llvm/trunk/test/CodeGen/ARM/fold-zext-zextload.ll

; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s ; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
define <4 x i8> @i(<4 x i8>*) !dbg !8 { define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
%2 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14 %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0) ; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0)
; CHECK-NEXT: VMOVLuv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14 ; CHECK-NEXT: VMOVLuv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
; CHECK-NEXT: VMOVLuv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14 ; CHECK-NEXT: VMOVLuv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
%4 = udiv <4 x i8> %1, %3, !dbg !15
%3 = udiv <4 x i8> zeroinitializer, %2, !dbg !15 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !11, metadata !DIExpression()), !dbg !14
call void @llvm.dbg.value(metadata <4 x i8> %2, metadata !11, metadata !DIExpression()), !dbg !14 call void @llvm.dbg.value(metadata <4 x i8> %4, metadata !13, metadata !DIExpression()), !dbg !15
call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !13, metadata !DIExpression()), !dbg !15 ret <4 x i8> %4, !dbg !16
ret <4 x i8> %3, !dbg !16
} }
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.debugify = !{!0, !1, !2, !3} !llvm.debugify = !{!0, !1, !2, !3}
!llvm.module.flags = !{!4} !llvm.module.flags = !{!4}
!llvm.dbg.cu = !{!5} !llvm.dbg.cu = !{!5}
Show All 18 Lines

llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <4 x i8> @h(<4 x float> %v) { define <4 x i8> @h(<4 x float> %v) {
; CHECK: vcvt.{{[us]}}32.f32 ; CHECK: vcvt.{{[us]}}32.f32
; CHECK: vmovn.i32 ; CHECK: vmovn.i32
%1 = fptoui <4 x float> %v to <4 x i8> %1 = fptoui <4 x float> %v to <4 x i8>
ret <4 x i8> %1 ret <4 x i8> %1
} }
; CHECK-LABEL: i: ; CHECK-LABEL: i:
define <4 x i8> @i(<4 x i8>* %x) { define <4 x i8> @i(<4 x i8>* %x, <4 x i8> %y) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON ; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores ; instructions is bad on some cores
; CHECK: vld1 ; CHECK: vld1
; CHECK: vmovl.s8 ; CHECK: vmovl.s8
; CHECK: vmovl.s16 ; CHECK: vmovl.s16
; CHECK: vrecpe ; CHECK: vrecpe
; CHECK: vrecps ; CHECK: vrecps
; CHECK: vmul ; CHECK: vmul
; CHECK: vmovn ; CHECK: vmovn
%1 = load <4 x i8>, <4 x i8>* %x, align 4 %1 = load <4 x i8>, <4 x i8>* %x, align 4
%2 = sdiv <4 x i8> zeroinitializer, %1 %2 = sdiv <4 x i8> %y, %1
ret <4 x i8> %2 ret <4 x i8> %2
} }
; CHECK-LABEL: j: ; CHECK-LABEL: j:
define <4 x i32> @j(<4 x i8>* %in) nounwind { define <4 x i32> @j(<4 x i8>* %in) nounwind {
; CHECK: vld1 ; CHECK: vld1
; CHECK: vmovl.u8 ; CHECK: vmovl.u8
; CHECK: vmovl.u16 ; CHECK: vmovl.u16
; CHECK-NOT: vand ; CHECK-NOT: vand
%1 = load <4 x i8>, <4 x i8>* %in, align 4 %1 = load <4 x i8>, <4 x i8>* %in, align 4
%2 = zext <4 x i8> %1 to <4 x i32> %2 = zext <4 x i8> %1 to <4 x i32>
ret <4 x i32> %2 ret <4 x i32> %2
} }