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Differential D53423

[llvm-exegesis] X87 RFP setup code.
ClosedPublic

Authored by courbet on Oct 19 2018, 2:19 AM.

Details

Reviewers
gchatelet
Commits
rGc51f45239d7d: [llvm-exegesis] X87 RFP setup code.
rL344779: [llvm-exegesis] X87 RFP setup code.
Summary

This was lost during refactoring in rL342644.

Fix and simplify simplify value size handling: always go through a 80 bit value,
because the value can be 1 byte). Add unit tests.

Diff Detail

Event Timeline

courbet created this revision.Oct 19 2018, 2:19 AM
Herald added a subscriber: tschuett. · View Herald TranscriptOct 19 2018, 2:19 AM
Harbormaster completed remote builds in B23928: Diff 170168.Oct 19 2018, 2:19 AM
gchatelet accepted this revision.Oct 19 2018, 2:50 AM
gchatelet added inline comments.
tools/llvm-exegesis/lib/X86/Target.cpp
186

kF80Bytes so it makes more sense to use LD_F80m afterwards

unittests/tools/llvm-exegesis/X86/TargetTest.cpp
299

Can you add a comment for all non-80bits tests to explain why we put an 80bits value on the stack?

This revision is now accepted and ready to land.Oct 19 2018, 2:50 AM
courbet updated this revision to Diff 170174.Oct 19 2018, 2:58 AM
courbet marked 2 inline comments as done.

address comments

Harbormaster completed remote builds in B23931: Diff 170174.Oct 19 2018, 2:58 AM
Closed by commit rL344779: [llvm-exegesis] X87 RFP setup code. (authored by courbet). · Explain WhyOct 19 2018, 2:58 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
tools/
llvm-exegesis/
lib/
X86/
40 lines
unittests/
tools/
llvm-exegesis/
X86/
51 lines

Diff 170168

tools/llvm-exegesis/lib/X86/Target.cpp

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Lines std::vector<llvm::MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth,
assert((RegBitWidth & 7) == 0 && assert((RegBitWidth & 7) == 0 &&
"RegBitWidth must be a multiple of 8 bits"); "RegBitWidth must be a multiple of 8 bits");
initStack(RegBitWidth / 8); initStack(RegBitWidth / 8);
add(loadToReg(Reg, Opcode)); add(loadToReg(Reg, Opcode));
add(releaseStackSpace(RegBitWidth / 8)); add(releaseStackSpace(RegBitWidth / 8));
return std::move(Instructions); return std::move(Instructions);
} }
std::vector<llvm::MCInst> std::vector<llvm::MCInst> loadX87STAndFinalize(unsigned Reg) {
loadX87AndFinalize(unsigned Reg, unsigned RegBitWidth, unsigned Opcode) { initStack(kX87Bytes);
gchateletUnsubmitted
Done
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kF80Bytes so it makes more sense to use LD_F80m afterwards

gchatelet: `kF80Bytes` so it makes more sense to use `LD_F80m` afterwards
assert((RegBitWidth & 7) == 0 && add(llvm::MCInstBuilder(llvm::X86::LD_F80m)
"RegBitWidth must be a multiple of 8 bits"); // Address = ESP
initStack(RegBitWidth / 8);
add(llvm::MCInstBuilder(Opcode)
.addReg(llvm::X86::RSP) // BaseReg .addReg(llvm::X86::RSP) // BaseReg
.addImm(1) // ScaleAmt .addImm(1) // ScaleAmt
.addReg(0) // IndexReg .addReg(0) // IndexReg
.addImm(0) // Disp .addImm(0) // Disp
.addReg(0)); // Segment .addReg(0)); // Segment
if (Reg != llvm::X86::ST0) if (Reg != llvm::X86::ST0)
add(llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(Reg)); add(llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(Reg));
add(releaseStackSpace(RegBitWidth / 8)); add(releaseStackSpace(kX87Bytes));
return std::move(Instructions);
}
std::vector<llvm::MCInst> loadX87FPAndFinalize(unsigned Reg) {
initStack(kX87Bytes);
add(llvm::MCInstBuilder(llvm::X86::LD_Fp80m)
.addReg(Reg)
// Address = ESP
.addReg(llvm::X86::RSP) // BaseReg
.addImm(1) // ScaleAmt
.addReg(0) // IndexReg
.addImm(0) // Disp
.addReg(0)); // Segment
add(releaseStackSpace(kX87Bytes));
return std::move(Instructions); return std::move(Instructions);
} }
std::vector<llvm::MCInst> popFlagAndFinalize() { std::vector<llvm::MCInst> popFlagAndFinalize() {
initStack(8); initStack(8);
add(llvm::MCInstBuilder(llvm::X86::POPF64)); add(llvm::MCInstBuilder(llvm::X86::POPF64));
return std::move(Instructions); return std::move(Instructions);
} }
private: private:
static constexpr const unsigned kX87Bytes = 10; // 80 bits.
ConstantInliner &add(const llvm::MCInst &Inst) { ConstantInliner &add(const llvm::MCInst &Inst) {
Instructions.push_back(Inst); Instructions.push_back(Inst);
return *this; return *this;
} }
void initStack(unsigned Bytes) { void initStack(unsigned Bytes) {
assert(Constant_.getBitWidth() <= Bytes * 8 && assert(Constant_.getBitWidth() <= Bytes * 8 &&
"Value does not have the correct size"); "Value does not have the correct size");
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines if (llvm::X86::VR256XRegClass.contains(Reg)) {
return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQU32Z256rm); return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQU32Z256rm);
if (STI.getFeatureBits()[llvm::X86::FeatureAVX]) if (STI.getFeatureBits()[llvm::X86::FeatureAVX])
return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQUYrm); return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQUYrm);
} }
if (llvm::X86::VR512RegClass.contains(Reg)) if (llvm::X86::VR512RegClass.contains(Reg))
if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) if (STI.getFeatureBits()[llvm::X86::FeatureAVX512])
return CI.loadAndFinalize(Reg, 512, llvm::X86::VMOVDQU32Zrm); return CI.loadAndFinalize(Reg, 512, llvm::X86::VMOVDQU32Zrm);
if (llvm::X86::RSTRegClass.contains(Reg)) { if (llvm::X86::RSTRegClass.contains(Reg)) {
if (Value.getBitWidth() == 32) return CI.loadX87STAndFinalize(Reg);
return CI.loadX87AndFinalize(Reg, 32, llvm::X86::LD_F32m); }
if (Value.getBitWidth() == 64) if (llvm::X86::RFP32RegClass.contains(Reg) ||
return CI.loadX87AndFinalize(Reg, 64, llvm::X86::LD_F64m); llvm::X86::RFP64RegClass.contains(Reg) ||
if (Value.getBitWidth() == 80) llvm::X86::RFP80RegClass.contains(Reg)) {
return CI.loadX87AndFinalize(Reg, 80, llvm::X86::LD_F80m); return CI.loadX87FPAndFinalize(Reg);
} }
if (Reg == llvm::X86::EFLAGS) if (Reg == llvm::X86::EFLAGS)
return CI.popFlagAndFinalize(); return CI.popFlagAndFinalize();
return {}; // Not yet implemented. return {}; // Not yet implemented.
} }
std::unique_ptr<SnippetGenerator> std::unique_ptr<SnippetGenerator>
createLatencySnippetGenerator(const LLVMState &State) const override { createLatencySnippetGenerator(const LLVMState &State) const override {
Show All 25 Lines

unittests/tools/llvm-exegesis/X86/TargetTest.cpp

Show First 20 Lines • Show All 290 Lines • ▼ Show 20 Lines EXPECT_THAT(
IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 48), IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 48),
IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 52), IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 52),
IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 56), IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 56),
IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 60), IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 60),
IsMovValueFromStack(llvm::X86::VMOVDQU32Zrm, llvm::X86::ZMM0), IsMovValueFromStack(llvm::X86::VMOVDQU32Zrm, llvm::X86::ZMM0),
IsStackDeallocate(64)})); IsStackDeallocate(64)}));
} }
TEST_F(Core2TargetTest, SetRegToST0_32Bits) { TEST_F(Core2TargetTest, SetRegToST0_32Bits) {
gchateletUnsubmitted
Done
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Can you add a comment for all non-80bits tests to explain why we put an 80bits value on the stack?

gchatelet: Can you add a comment for all non-80bits tests to explain why we put an 80bits value on the…
EXPECT_THAT( EXPECT_THAT(
setRegTo(llvm::X86::ST0, APInt(32, 0x11112222ULL)), setRegTo(llvm::X86::ST0, APInt(32, 0x11112222ULL)),
ElementsAre(IsStackAllocate(4), ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0), IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
OpcodeIs(llvm::X86::LD_F32m), IsStackDeallocate(4))); IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
} }
TEST_F(Core2TargetTest, SetRegToST1_32Bits) { TEST_F(Core2TargetTest, SetRegToST1_32Bits) {
const MCInst CopySt0ToSt1 = const MCInst CopySt0ToSt1 =
llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(llvm::X86::ST1); llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(llvm::X86::ST1);
EXPECT_THAT( EXPECT_THAT(
setRegTo(llvm::X86::ST1, APInt(32, 0x11112222ULL)), setRegTo(llvm::X86::ST1, APInt(32, 0x11112222ULL)),
ElementsAre(IsStackAllocate(4), ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0), IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
OpcodeIs(llvm::X86::LD_F32m), CopySt0ToSt1, IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
IsStackDeallocate(4))); IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
OpcodeIs(llvm::X86::LD_F80m), CopySt0ToSt1,
IsStackDeallocate(10)));
} }
TEST_F(Core2TargetTest, SetRegToST0_64Bits) { TEST_F(Core2TargetTest, SetRegToST0_64Bits) {
EXPECT_THAT( EXPECT_THAT(
setRegTo(llvm::X86::ST0, APInt(64, 0x1111222233334444ULL)), setRegTo(llvm::X86::ST0, APInt(64, 0x1111222233334444ULL)),
ElementsAre(IsStackAllocate(8), ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0), IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0),
IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4), IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4),
OpcodeIs(llvm::X86::LD_F64m), IsStackDeallocate(8))); IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
} }
TEST_F(Core2TargetTest, SetRegToST0_80Bits) { TEST_F(Core2TargetTest, SetRegToST0_80Bits) {
EXPECT_THAT( EXPECT_THAT(
setRegTo(llvm::X86::ST0, APInt(80, "11112222333344445555", 16)), setRegTo(llvm::X86::ST0, APInt(80, "11112222333344445555", 16)),
ElementsAre(IsStackAllocate(10), ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0), IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0),
IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4), IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4),
IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8), IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8),
OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10))); OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10)));
} }
TEST_F(Core2TargetTest, SetRegToFP0_80Bits) {
EXPECT_THAT(
setRegTo(llvm::X86::FP0, APInt(80, "11112222333344445555", 16)),
ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0),
IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4),
IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8),
OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10)));
}
TEST_F(Core2TargetTest, SetRegToFP1_32Bits) {
EXPECT_THAT(
setRegTo(llvm::X86::FP1, APInt(32, 0x11112222ULL)),
ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0),
IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
OpcodeIs(llvm::X86::LD_Fp80m),
IsStackDeallocate(10)));
}
TEST_F(Core2TargetTest, SetRegToFP1_4Bits) {
EXPECT_THAT(
setRegTo(llvm::X86::FP1, APInt(4, 0x1ULL)),
ElementsAre(IsStackAllocate(10),
IsMovValueToStack(llvm::X86::MOV32mi, 0x00000001UL, 0),
IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4),
IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8),
OpcodeIs(llvm::X86::LD_Fp80m),
IsStackDeallocate(10)));
}
} // namespace } // namespace
} // namespace exegesis } // namespace exegesis