[lbc++abi] [unwinder] Support Cortex-m0

[jroelofs]

Summary

Also has a pair of fixes for armv4t. Let me know if you'd like those in a separate patch.

[jroelofs]

[Same patch, better diff]

[compnerd]

src/Unwind/UnwindRegistersSave.S

335

Doesn't this change the behavior for __ARM_ARCH >= 7?

352

Doesn't this change the behavior for __ARM_ARCH >= 7?

368

This also doesn't work for ARMv7. Consider ARM VFPv3-d16 (e.g. Tegra2) ... vstmia r0, {d16-d31} refers to a non-existent register set.

392

Do all CPUs have the wmmxt register set? It might be more prudent to move this out into a separate translation unit that is linked in if the target supports iwmmxt.

419

Oh joy ... this is scary.

Do we have some guarantee that they won't accidentally use long rather than int?

420

Similar to above.

[rengolin]

src/Unwind/UnwindRegistersRestore.S

341

I think we should use the same trick we used in other ARM files, to define a macro that is set by the arch for returning.

355

Do you want to export the symbols (unwindVFP) but have it do nothing? Is it even possible to try to unwind VFP on v6M? Shouldn't this be a compilation error?

380

This macro is in a different order than the one above, and will generate vldmia on v6M which will fail.

src/Unwind/UnwindRegistersSave.S

285

Maybe we should also have a macro that will use thumb on thumb-only platforms like v6M and v6M variants. That would have to be accompanied by changes to other areas, making them Thumb/2 friendly (like the ones you add here).

368

And this is exactly the opposite as the other, which would just get "bx lr" on ARMv6M

[jroelofs]

Sorry about the hideously bad merge....

src/Unwind/UnwindRegistersRestore.S

341

Sounds like a good idea to me.

355

I think that this will never get called on v6m because it doesn't have vfp registers, so the compiler will never issue the unwind opcodes that trigger this being called. Maybe that warrants having the body be:

assert(false)

?

This could be completely ifdef'd out on v6m, but that would mean ifdefing out the callers too, which would be a bit ugly. It does save a few bytes though....

380

Oops, bad merge. Yeah, they should be transposed.

397

Another bad merge. Transpose this with the line above it.

440

Another bad merge / patch cut. I didn't intend to include the s/MMXControlEPj/MMXControlEPm/ change.

src/Unwind/UnwindRegistersSave.S

285

like a LIBUNWIND_THUMB_ONLY flag?

335

Another bad merge. This line, and the one above it should be transposed.

352

Another bad merge. This line, and the one above it should be transposed.

368

Conditions on this one should be flipped.... oops.

382

Maybe this should use that RETURN macro @rengolin suggests?

392

I think the idea here (before my change) was that if you were to build this library with -march=armv5t then you could either link it with code for a PXA270 and get something that would work on that arch, or link it with normal v5t code and get something that would work on a vanilla v5t board.

With my change I am trying to be conservative... I don't know whether there are any v6m's with iwmmx support, but if there are, then this should DTRT.

419

Oops, another bad patch cut. The s/saveiWMMXControlEPj/saveiWMMXControlEPm/ change is part of a different patch where I change the type of the argument to void*.

[jroelofs]

Move return instructions into ARM_RETURN macro.
Add ARM_THUMB1_ONLY guard.
Add ARM_HAS_NO_VFP guard.

[jroelofs]

Forgot an #endif. Sorry about the spam.

[compnerd]

Please drop ARM_RETURN and use JMP(lr). That is duplicating an existing macro which is already in use.

Im not sure I understand why you are creating a new macro for the thumb check. __ARM_ARCH_ISA_THUMB == 1 is sufficient to identify if you only have Thumb-1. However, do you really want to use thumb instructions if you only have Thumb-1?

I dont understand the need for the ARM_HAS_NO_VFP. Isn't __VFP_FP__ usable for your check there? I don't think we need yet another macro, particularly if there is one that is defined by the compiler.

Finally, is __ARM_WMMX supposed to be defined for ARMv6M/s?

[jroelofs]

In D5314#14, @compnerd wrote:

Please drop ARM_RETURN and use JMP(lr). That is duplicating an existing macro which is already in use.

Sure, I'll copy over the ARM part of compiler_rt's assembly.h

Im not sure I understand why you are creating a new macro for the thumb check. __ARM_ARCH_ISA_THUMB == 1 is sufficient to identify if you only have Thumb-1. However, do you really want to use thumb instructions if you only have Thumb-1?

Sorry, bad name. What I meant here is to have a macro that means "doesn't have the ARM instruction set" (i.e. v6m, v6sm, v7m). I think this is what I actually mean:

#if !defined(__ARM_ARCH_ISA_ARM)

I dont understand the need for the ARM_HAS_NO_VFP. Isn't __VFP_FP__ usable for your check there? I don't think we need yet another macro, particularly if there is one that is defined by the compiler.

No, __VFP_FP__ isn't the right one for this. The best reference I can find for what that one means is this: https://wiki.debian.org/ArmEabiPort "Note that __VFP_FP__ does not mean that VFP code generation has been selected. It only speaks of the floating point data format in use and is normally set when soft-float has been selected."

After some digging around in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf I think __ARM_FP is the right one to use, but it looks like clang doesn't ever define that one on 32bit arm. I should probably fix that first....

Finally, is __ARM_WMMX supposed to be defined for ARMv6M/s?

I don't know of any v6m/v6sm's with iWMMX instructions (and therefore __ARM_WMMX), but it might be possible that could exist, hence the:

#if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || __ARM_WMMX

My assembler barfs on the coprocessor instructions in those blocks, so maybe it's not possible to have iWMMX instructions on a v6m part?

[jroelofs]

Address a few of @compnerd's comments. This is contingent on fixing __ARM_FP in clang.

[compnerd]

assembly.h

65 ↗

(On Diff #13753)

The whole block of __ARM_ARCH seems incorrect to me. What compiler are you trying to support? Both clang and gcc have supported this part of the ACLE for some time now.

[jroelofs]

Dump the __ARM_ARCH ACLE shims that were copy-pasted from compiler_rt's assembly.h (and have been deleted there).

[rengolin]

Hi Jon,

Looks ok to me, but please wait for Saleem's blessing.

cheers,
--renato

[jroelofs]

@compnerd: ping

[compnerd]

Thanks for making all the adjustments!

[jroelofs]

Thanks for the review! Committed as r218869.

Jon

src/Unwind/UnwindRegistersRestore.S

DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind15Registers_arm646jumptoEv)
   ldr    d30,     [x0, #0x200]
   ldr    d31,     [x0, #0x208]
 
   ldp    x0, x1,  [x0, #0x000]  ; restore x0,x1
   ret    lr            ; jump to pc
 
 #elif __arm__ && !__APPLE__
 
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__)
+  .thumb
+#endif
+
 @
 @ void libunwind::Registers_arm::restoreCoreAndJumpTo()
 @
 @ On entry:
 @  thread_state pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
+  ldr r2, [r0, #52]
+  ldr r3, [r0, #60]
+  mov sp, r2
+  mov lr, r3         @ restore pc into lr
+  ldm r0, {r0-r7}
+#else
   @ Use lr as base so that r0 can be restored.
   mov lr, r0
   @ 32bit thumb-2 restrictions for ldm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) and lr (r14) cannot both be in the list in an LDM instruction
   ldm lr, {r0-r12}
   ldr sp, [lr, #52]
   ldr lr, [lr, #60]  @ restore pc into lr
-#if __ARM_ARCH > 4
+#endif
+#if __ARM_ARCH > 4 || __ARM_ARCH_4T__
   bx lr
 #else
   mov pc, lr
 #endif
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMDEPy)
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)
   @ VFP and iwMMX instructions are only available when compiling with the flags
-  @ that enable them. We don't want to do that in the library (because we don't
+  @ that enable them. We do not want to do that in the library (because we do not
   @ want the compiler to generate instructions that access those) but this is
   @ only accessed if the personality routine needs these registers. Use of
   @ these registers implies they are, actually, available on the target, so
   @ it's ok to execute.
   @ So, generate the instruction using the corresponding coprocessor mnemonic.
 #if __ARM_ARCH < 7
   ldc p11, cr0, [r0], {0x20}  @ fldmiad r0, {d0-d15}
 #else
   vldmia r0, {d0-d15}
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMX(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
 #if __ARM_ARCH < 7
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)
   ldc p11, cr0, [r0], {0x21}  @ fldmiax r0, {d0-d15}
 #else
   vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::restoreVFPv3(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
 #if __ARM_ARCH < 7
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)
   ldcl p11, cr0, [r0], {0x20}  @ vldm r0, {d16-d31}
 #else
   vldmia r0, {d16-d31}
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::restoreiWMMX(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreiWMMXEPy)
+#if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || __ARM_WMMX
   ldcl p1, cr0, [r0], #8  @ wldrd wR0, [r0], #8
   ldcl p1, cr1, [r0], #8  @ wldrd wR1, [r0], #8
   ldcl p1, cr2, [r0], #8  @ wldrd wR2, [r0], #8
   ldcl p1, cr3, [r0], #8  @ wldrd wR3, [r0], #8
   ldcl p1, cr4, [r0], #8  @ wldrd wR4, [r0], #8
   ldcl p1, cr5, [r0], #8  @ wldrd wR5, [r0], #8
   ldcl p1, cr6, [r0], #8  @ wldrd wR6, [r0], #8
   ldcl p1, cr7, [r0], #8  @ wldrd wR7, [r0], #8
   ldcl p1, cr8, [r0], #8  @ wldrd wR8, [r0], #8
   ldcl p1, cr9, [r0], #8  @ wldrd wR9, [r0], #8
   ldcl p1, cr10, [r0], #8  @ wldrd wR10, [r0], #8
   ldcl p1, cr11, [r0], #8  @ wldrd wR11, [r0], #8
   ldcl p1, cr12, [r0], #8  @ wldrd wR12, [r0], #8
   ldcl p1, cr13, [r0], #8  @ wldrd wR13, [r0], #8
   ldcl p1, cr14, [r0], #8  @ wldrd wR14, [r0], #8
   ldcl p1, cr15, [r0], #8  @ wldrd wR15, [r0], #8
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::restoreiWMMXControl(unw_uint32_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreiWMMXControlEPj)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreiWMMXControlEPm)
+#if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || __ARM_WMMX
   ldc2 p1, cr8, [r0], #4  @ wldrw wCGR0, [r0], #4
   ldc2 p1, cr9, [r0], #4  @ wldrw wCGR1, [r0], #4
   ldc2 p1, cr10, [r0], #4  @ wldrw wCGR2, [r0], #4
   ldc2 p1, cr11, [r0], #4  @ wldrw wCGR3, [r0], #4
+#endif
   mov pc, lr
 
 #endif

src/Unwind/UnwindRegistersSave.S

DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
   stp    d28,d29, [x0, #0x1F0]
   str    d30,     [x0, #0x200]
   str    d31,     [x0, #0x208]
   ldr    x0, #0      ; return UNW_ESUCCESS
   ret
 
 #elif __arm__ && !__APPLE__
 
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
+  .thumb
+#endif
+
 @
 @ extern int unw_getcontext(unw_context_t* thread_state)
 @
 @ On entry:
 @  thread_state pointer is in r0
 @ 
 @ Per EHABI #4.7 this only saves the core integer registers.
 @ EHABI #7.4.5 notes that in general all VRS registers should be restored
 @ however this is very hard to do for VFP registers because it is unknown
 @ to the lbirary how many registers are implemented by the architecture.
 @ Instead, VFP registers are demand saved by logic external to unw_getcontext.
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
+  stm r0!, {r0-r7}
+  mov r2, sp
+  mov r3, lr
+  str r2, [r0, #52]
+  str r3, [r0, #56]
+  str r3, [r0, #60]  @ store return address as pc
+#else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
+#endif
   mov r0, #0         @ return UNW_ESUCCESS
-#if __ARM_ARCH > 4
+#if __ARM_ARCH > 4 || __ARM_ARCH_4T__
   bx lr
 #else
   mov pc, lr
 #endif
 
 @
 @ static void libunwind::Registers_arm::saveVFPWithFSTMD(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPy)
 #if __ARM_ARCH < 7
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
   stc p11, cr0, [r0], {0x20}  @ fstmiad r0, {d0-d15}
 #else
   vstmia r0, {d0-d15}
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::saveVFPWithFSTMX(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPy)
 #if __ARM_ARCH < 7
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
   stc p11, cr0, [r0], {0x21}  @ fstmiax r0, {d0-d15}
 #else
   vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::saveVFPv3(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm9saveVFPv3EPy)
+#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) 
   @ VFP and iwMMX instructions are only available when compiling with the flags
-  @ that enable them. We don't want to do that in the library (because we don't
+  @ that enable them. We do not want to do that in the library (because we do not
   @ want the compiler to generate instructions that access those) but this is
   @ only accessed if the personality routine needs these registers. Use of
   @ these registers implies they are, actually, available on the target, so
   @ it's ok to execute.
   @ So, generate the instructions using the corresponding coprocessor mnemonic.
 #if __ARM_ARCH < 7
   stcl p11, cr0, [r0], {0x20}  @ vstm r0, {d16-d31}
 #else
   vstmia r0, {d16-d31}
 #endif
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::saveiWMMX(unw_fpreg_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm9saveiWMMXEPy)
+#if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || __ARM_WMMX
   stcl p1, cr0, [r0], #8  @ wstrd wR0, [r0], #8
   stcl p1, cr1, [r0], #8  @ wstrd wR1, [r0], #8
   stcl p1, cr2, [r0], #8  @ wstrd wR2, [r0], #8
   stcl p1, cr3, [r0], #8  @ wstrd wR3, [r0], #8
   stcl p1, cr4, [r0], #8  @ wstrd wR4, [r0], #8
   stcl p1, cr5, [r0], #8  @ wstrd wR5, [r0], #8
   stcl p1, cr6, [r0], #8  @ wstrd wR6, [r0], #8
   stcl p1, cr7, [r0], #8  @ wstrd wR7, [r0], #8
   stcl p1, cr8, [r0], #8  @ wstrd wR8, [r0], #8
   stcl p1, cr9, [r0], #8  @ wstrd wR9, [r0], #8
   stcl p1, cr10, [r0], #8  @ wstrd wR10, [r0], #8
   stcl p1, cr11, [r0], #8  @ wstrd wR11, [r0], #8
   stcl p1, cr12, [r0], #8  @ wstrd wR12, [r0], #8
   stcl p1, cr13, [r0], #8  @ wstrd wR13, [r0], #8
   stcl p1, cr14, [r0], #8  @ wstrd wR14, [r0], #8
   stcl p1, cr15, [r0], #8  @ wstrd wR15, [r0], #8
+#endif
   mov pc, lr
 
 @
 @ static void libunwind::Registers_arm::saveiWMMXControl(unw_uint32_t* values)
 @
 @ On entry:
 @  values pointer is in r0
 @
   .p2align 2
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveiWMMXControlEPj)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveiWMMXControlEPm)
+#if (!defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_6SM__)) || __ARM_WMMX
   stc2 p1, cr8, [r0], #4  @ wstrw wCGR0, [r0], #4
   stc2 p1, cr9, [r0], #4  @ wstrw wCGR1, [r0], #4
   stc2 p1, cr10, [r0], #4  @ wstrw wCGR2, [r0], #4
   stc2 p1, cr11, [r0], #4  @ wstrw wCGR3, [r0], #4
+#endif
   mov pc, lr
 
 #endif