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[X86] X86ISelLowering: combineAndIntoBEXTR(): support shifted mask.
AbandonedPublic

Authored by lebedev.ri on Oct 10 2018, 7:28 AM.

Details

Summary

Continuation of D52426.

As discussed in PR38938,
we fail to emit BEXTR if the mask is shifted.
We can't deal with that in X86DAGToDAGISel before the address mode for the inc is selected,
and we can't really do it in the normal DAGCombine, because we don't have generic ISD::BitFieldExtract node,
and if we simply turn the shifted mask into a normal mask + shift-left, it will be folded back.
So it would seem X86ISelLowering is the place to handle this.

Here, we extend the combine to actually support the pattern with shifted mask.

Diff Detail

Repository
rL LLVM

Event Timeline

@RKSimon note that only this differential does finally solve the PR38938.

craig.topper added inline comments.Oct 10 2018, 12:05 PM
test/CodeGen/X86/extract-bits.ll
5843

In a placement that isn't register constrained where the "mov %edi, %eax" copy in the original code doesn't need to exist, isn't this code worse?

For example I would expect this to from 3 instructions to 4 with this patch.

define void @foo(i32 %arg, i32* %ptr) {
  %tmp0 = lshr i32 %arg, 19
  %tmp1 = and i32 %tmp0, 1023
  %tmp2 = shl i32 %tmp1, 2
  store i32 %tmp2, i32* %ptr
  ret void
}

Rebased, more tests.

test/CodeGen/X86/extract-bits.ll
5843

Tests added, but did not analyze them yet.

lebedev.ri added inline comments.Oct 10 2018, 2:08 PM
test/CodeGen/X86/extract-bits.ll
6232

Hm, indeed, these tests degrade.
I don't have any good ideas on how to avoid this.

lebedev.ri abandoned this revision.Oct 11 2018, 11:08 AM

Superseeded by D53126.