[llvm-exegesis] Remove unused variable, add more semantic to Instruction.

[courbet]

tools/llvm-exegesis/lib/MCInstrDescView.h

116 ↗

(On Diff #168942)

alias*

120 ↗

(On Diff #168942)

ditto

[gchatelet]

• Fix aliases/alias

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h

struct Variable {
   // Returns the index of the Operand linked to this Variable.
   unsigned getPrimaryOperandIndex() const;
 
   // Returns whether this Variable has more than one Operand linked to it.
   bool hasTiedOperands() const;
 
   // The indices of the operands tied to this Variable.
   llvm::SmallVector<unsigned, 2> TiedOperands;
-  llvm::MCOperand AssignedValue;
+
   // The index of this Variable in Instruction.Variables and its associated
   // Value in InstructionBuilder.VariableValues.
   int Index = -1;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.
 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.

 struct Instruction {
   Instruction(const llvm::MCInstrDesc &MCInstrDesc,
               const RegisterAliasingTrackerCache &ATC);
 
   // Returns the Operand linked to this Variable.
   // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
   const Operand &getPrimaryOperand(const Variable &Var) const;
 
-  // Returns whether this instruction has Memory Operands.
-  // Repeating this instruction executes sequentially with an instruction that
-  // reads or write the same memory region.
-  bool hasMemoryOperands() const;
+  // Whether this instruction is self aliasing through its tied registers.
+  // Repeating this instruction is guaranteed to executes sequentially.
+  bool hasTiedRegisters() const;
 
   // Whether this instruction is self aliasing through its implicit registers.
   // Repeating this instruction is guaranteed to executes sequentially.
   bool hasAliasingImplicitRegisters() const;
 
-  // Whether this instruction is self aliasing through its tied registers.
-  // Repeating this instruction is guaranteed to executes sequentially.
-  bool hasTiedRegisters() const;
-
   // Whether this instruction is self aliasing through some registers.
   // Repeating this instruction may execute sequentially by picking aliasing
   // Use and Def registers. It may also execute in parallel by picking non
   // aliasing Use and Def registers.
   bool hasAliasingRegisters() const;
 
+  // Whether this instruction's implicit registers alias with OtherInstr's
+  // implicit registers.
+  bool hasAliasingImplicitRegistersThrough(const Instruction &OtherInstr) const;
+
+  // Whether this instruction's registers alias with OtherInstr's registers.
+  bool hasAliasingRegistersThrough(const Instruction &OtherInstr) const;
+
+  // Returns whether this instruction has Memory Operands.
+  // Repeating this instruction executes sequentially with an instruction that
+  // reads or write the same memory region.
+  bool hasMemoryOperands() const;
+
   // Convenient function to help with debugging.
   void dump(const llvm::MCRegisterInfo &RegInfo,
             llvm::raw_ostream &Stream) const;
 
   const llvm::MCInstrDesc *Description; // Never nullptr.
   llvm::SmallVector<Operand, 8> Operands;
   llvm::SmallVector<Variable, 4> Variables;
   llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp

return std::any_of(Operands.begin(), Operands.end(), [](const Operand &Op) {
     return Op.isReg() && Op.isExplicit() && Op.isMemory();
   });
 }
 
 bool Instruction::hasAliasingImplicitRegisters() const {
   return ImplDefRegs.anyCommon(ImplUseRegs);
 }
 
+bool Instruction::hasAliasingImplicitRegistersThrough(
+    const Instruction &OtherInstr) const {
+  return ImplDefRegs.anyCommon(OtherInstr.ImplUseRegs) &&
+         OtherInstr.ImplDefRegs.anyCommon(ImplUseRegs);
+}
+
+bool Instruction::hasAliasingRegistersThrough(
+    const Instruction &OtherInstr) const {
+  return AllDefRegs.anyCommon(OtherInstr.AllUseRegs) &&
+         OtherInstr.AllDefRegs.anyCommon(AllUseRegs);
+}
+
 bool Instruction::hasTiedRegisters() const {
   return llvm::any_of(
       Variables, [](const Variable &Var) { return Var.hasTiedOperands(); });
 }
 
 bool Instruction::hasAliasingRegisters() const {
   return AllDefRegs.anyCommon(AllUseRegs);
 }
if (Op.isReg()) {
                << ")";
     }
     if (Op.isTied())
       Stream << " TiedToOp" << Op.getTiedToIndex();
     Stream << "\n";
   }
   for (const auto &Var : Variables) {
     Stream << "- Var" << Var.getIndex();
+    Stream << " (";
     for (auto OperandIndex : Var.TiedOperands)
-      Stream << " Op" << OperandIndex;
+      Stream << "Op" << OperandIndex;
+    Stream << ")";
     Stream << "\n";
   }
   if (hasMemoryOperands())
     Stream << "- hasMemoryOperands\n";
   if (hasAliasingImplicitRegisters())
     Stream << "- hasAliasingImplicitRegisters (execution is always serial)\n";
   if (hasTiedRegisters())
     Stream << "- hasTiedRegisters (execution is always serial)\n";