[X86] Remove FeatureRTM from Skylake processor list

[thiagomacieira]

Summary

There are a LOT of Skylakes and later without TSX-NI. Examples:

• SKL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3-20-GHz-
• KBL: https://ark.intel.com/products/97540/Intel-Core-i7-7560U-Processor-4M-Cache-up-to-3-80-GHz-
• KBL-R: https://ark.intel.com/products/149091/Intel-Core-i7-8565U-Processor-8M-Cache-up-to-4-60-GHz-
• CNL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz

This feature seems to be present only on high-end desktop and server
chips (I can't find any SKX without). This commit leaves it disabled
for all processors, but can be re-enabled for specific builds with
-mrtm.

Matches https://reviews.llvm.org/D53041

[craig.topper]

LGTM

[lebedev.ri]

lib/Basic/Targets/X86.cpp

169 ↗

(On Diff #168868)

high-end desktop and server chips (I can't find any SKX without).

Are you sure you didn't want to move it into an else of this if() ?

[craig.topper]

lib/Basic/Targets/X86.cpp

169 ↗

(On Diff #168868)

This commit leaves it disabled for all processors, but can be re-enabled for specific builds with -mrtm.

So I think this was intended.

[thiagomacieira]

lib/Basic/Targets/X86.cpp

169 ↗

(On Diff #168868)

I'm sure I didn't want to :-) Do you want me to do that? And do you want me to do it for IcelakeServer too?

This matches GCC's behaviour:

$ gcc -march=skylake-avx512 -dM -E -xc /dev/null | grep -c RTM
0

[craig.topper]

But there is definitely at least one test that needs to be updated. @thiagomacieira, can update them or would you like me to?

lib/Basic/Targets/X86.cpp

169 ↗

(On Diff #168868)

It's also consistent with gcc based on grepping for _RTM_ in their predefined macro output. https://godbolt.org/z/dtfrQU They don't infer it from -mcpu=skylake-avx512, but do when adding -mrtm

[thiagomacieira]

Added test update

[craig.topper]

LGTM

[lebedev.ri]

lib/Basic/Targets/X86.cpp

169 ↗

(On Diff #168868)

I'm sure I didn't want to :-) Do you want me to do that?

Not really, just looked weird.

cfe/trunk/lib/Basic/Targets/X86.cpp

case CK_SkylakeServer:
     LLVM_FALLTHROUGH;
   case CK_SkylakeClient:
     setFeatureEnabledImpl(Features, "xsavec", true);
     setFeatureEnabledImpl(Features, "xsaves", true);
     setFeatureEnabledImpl(Features, "mpx", true);
     if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX
       setFeatureEnabledImpl(Features, "sgx", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
-    setFeatureEnabledImpl(Features, "rtm", true);
     setFeatureEnabledImpl(Features, "aes", true);
     LLVM_FALLTHROUGH;
   case CK_Broadwell:
     setFeatureEnabledImpl(Features, "rdseed", true);
     setFeatureEnabledImpl(Features, "adx", true);
     setFeatureEnabledImpl(Features, "prfchw", true);
     LLVM_FALLTHROUGH;
   case CK_Haswell:

cfe/trunk/test/Preprocessor/predefined-arch-macros.c

 // CHECK_SKL_M32: #define __MMX__ 1
 // CHECK_SKL_M32: #define __MOVBE__ 1
 // CHECK_SKL_M32: #define __MPX__ 1
 // CHECK_SKL_M32: #define __PCLMUL__ 1
 // CHECK_SKL_M32: #define __POPCNT__ 1
 // CHECK_SKL_M32: #define __PRFCHW__ 1
 // CHECK_SKL_M32: #define __RDRND__ 1
 // CHECK_SKL_M32: #define __RDSEED__ 1
-// CHECK_SKL_M32: #define __RTM__ 1
 // CHECK_SKL_M32: #define __SGX__ 1
 // CHECK_SKL_M32: #define __SSE2__ 1
 // CHECK_SKL_M32: #define __SSE3__ 1
 // CHECK_SKL_M32: #define __SSE4_1__ 1
 // CHECK_SKL_M32: #define __SSE4_2__ 1
 // CHECK_SKL_M32: #define __SSE__ 1
 // CHECK_SKL_M32: #define __SSSE3__ 1
 // CHECK_SKL_M32: #define __XSAVEC__ 1

 // CHECK_SKL_M64: #define __MMX__ 1
 // CHECK_SKL_M64: #define __MOVBE__ 1
 // CHECK_SKL_M64: #define __MPX__ 1
 // CHECK_SKL_M64: #define __PCLMUL__ 1
 // CHECK_SKL_M64: #define __POPCNT__ 1
 // CHECK_SKL_M64: #define __PRFCHW__ 1
 // CHECK_SKL_M64: #define __RDRND__ 1
 // CHECK_SKL_M64: #define __RDSEED__ 1
-// CHECK_SKL_M64: #define __RTM__ 1
 // CHECK_SKL_M64: #define __SGX__ 1
 // CHECK_SKL_M64: #define __SSE2_MATH__ 1
 // CHECK_SKL_M64: #define __SSE2__ 1
 // CHECK_SKL_M64: #define __SSE3__ 1
 // CHECK_SKL_M64: #define __SSE4_1__ 1
 // CHECK_SKL_M64: #define __SSE4_2__ 1
 // CHECK_SKL_M64: #define __SSE_MATH__ 1
 // CHECK_SKL_M64: #define __SSE__ 1

 // CHECK_KNL_M32: #define __LZCNT__ 1
 // CHECK_KNL_M32: #define __MMX__ 1
 // CHECK_KNL_M32: #define __MOVBE__ 1
 // CHECK_KNL_M32: #define __PCLMUL__ 1
 // CHECK_KNL_M32: #define __POPCNT__ 1
 // CHECK_KNL_M32: #define __PREFETCHWT1__ 1
 // CHECK_KNL_M32: #define __PRFCHW__ 1
 // CHECK_KNL_M32: #define __RDRND__ 1
-// CHECK_KNL_M32: #define __RTM__ 1
 // CHECK_KNL_M32: #define __SSE2__ 1
 // CHECK_KNL_M32: #define __SSE3__ 1
 // CHECK_KNL_M32: #define __SSE4_1__ 1
 // CHECK_KNL_M32: #define __SSE4_2__ 1
 // CHECK_KNL_M32: #define __SSE__ 1
 // CHECK_KNL_M32: #define __SSSE3__ 1
 // CHECK_KNL_M32: #define __XSAVEOPT__ 1
 // CHECK_KNL_M32: #define __XSAVE__ 1

 // CHECK_KNL_M64: #define __LZCNT__ 1
 // CHECK_KNL_M64: #define __MMX__ 1
 // CHECK_KNL_M64: #define __MOVBE__ 1
 // CHECK_KNL_M64: #define __PCLMUL__ 1
 // CHECK_KNL_M64: #define __POPCNT__ 1
 // CHECK_KNL_M64: #define __PREFETCHWT1__ 1
 // CHECK_KNL_M64: #define __PRFCHW__ 1
 // CHECK_KNL_M64: #define __RDRND__ 1
-// CHECK_KNL_M64: #define __RTM__ 1
 // CHECK_KNL_M64: #define __SSE2_MATH__ 1
 // CHECK_KNL_M64: #define __SSE2__ 1
 // CHECK_KNL_M64: #define __SSE3__ 1
 // CHECK_KNL_M64: #define __SSE4_1__ 1
 // CHECK_KNL_M64: #define __SSE4_2__ 1
 // CHECK_KNL_M64: #define __SSE_MATH__ 1
 // CHECK_KNL_M64: #define __SSE__ 1
 // CHECK_KNL_M64: #define __SSSE3__ 1

 // CHECK_KNM_M32: #define __LZCNT__ 1
 // CHECK_KNM_M32: #define __MMX__ 1
 // CHECK_KNM_M32: #define __MOVBE__ 1
 // CHECK_KNM_M32: #define __PCLMUL__ 1
 // CHECK_KNM_M32: #define __POPCNT__ 1
 // CHECK_KNM_M32: #define __PREFETCHWT1__ 1
 // CHECK_KNM_M32: #define __PRFCHW__ 1
 // CHECK_KNM_M32: #define __RDRND__ 1
-// CHECK_KNM_M32: #define __RTM__ 1
 // CHECK_KNM_M32: #define __SSE2__ 1
 // CHECK_KNM_M32: #define __SSE3__ 1
 // CHECK_KNM_M32: #define __SSE4_1__ 1
 // CHECK_KNM_M32: #define __SSE4_2__ 1
 // CHECK_KNM_M32: #define __SSE__ 1
 // CHECK_KNM_M32: #define __SSSE3__ 1
 // CHECK_KNM_M32: #define __XSAVEOPT__ 1
 // CHECK_KNM_M32: #define __XSAVE__ 1

 // CHECK_KNM_M64: #define __LZCNT__ 1
 // CHECK_KNM_M64: #define __MMX__ 1
 // CHECK_KNM_M64: #define __MOVBE__ 1
 // CHECK_KNM_M64: #define __PCLMUL__ 1
 // CHECK_KNM_M64: #define __POPCNT__ 1
 // CHECK_KNM_M64: #define __PREFETCHWT1__ 1
 // CHECK_KNM_M64: #define __PRFCHW__ 1
 // CHECK_KNM_M64: #define __RDRND__ 1
-// CHECK_KNM_M64: #define __RTM__ 1
 // CHECK_KNM_M64: #define __SSE2_MATH__ 1
 // CHECK_KNM_M64: #define __SSE2__ 1
 // CHECK_KNM_M64: #define __SSE3__ 1
 // CHECK_KNM_M64: #define __SSE4_1__ 1
 // CHECK_KNM_M64: #define __SSE4_2__ 1
 // CHECK_KNM_M64: #define __SSE_MATH__ 1
 // CHECK_KNM_M64: #define __SSE__ 1
 // CHECK_KNM_M64: #define __SSSE3__ 1

 // CHECK_SKX_M32: #define __MOVBE__ 1
 // CHECK_SKX_M32: #define __MPX__ 1
 // CHECK_SKX_M32: #define __PCLMUL__ 1
 // CHECK_SKX_M32: #define __PKU__ 1
 // CHECK_SKX_M32: #define __POPCNT__ 1
 // CHECK_SKX_M32: #define __PRFCHW__ 1
 // CHECK_SKX_M32: #define __RDRND__ 1
 // CHECK_SKX_M32: #define __RDSEED__ 1
-// CHECK_SKX_M32: #define __RTM__ 1
 // CHECK_SKX_M32-NOT: #define __SGX__ 1
 // CHECK_SKX_M32: #define __SSE2__ 1
 // CHECK_SKX_M32: #define __SSE3__ 1
 // CHECK_SKX_M32: #define __SSE4_1__ 1
 // CHECK_SKX_M32: #define __SSE4_2__ 1
 // CHECK_SKX_M32: #define __SSE__ 1
 // CHECK_SKX_M32: #define __SSSE3__ 1
 // CHECK_SKX_M32: #define __XSAVEC__ 1

 // CHECK_SKX_M64: #define __MOVBE__ 1
 // CHECK_SKX_M64: #define __MPX__ 1
 // CHECK_SKX_M64: #define __PCLMUL__ 1
 // CHECK_SKX_M64: #define __PKU__ 1
 // CHECK_SKX_M64: #define __POPCNT__ 1
 // CHECK_SKX_M64: #define __PRFCHW__ 1
 // CHECK_SKX_M64: #define __RDRND__ 1
 // CHECK_SKX_M64: #define __RDSEED__ 1
-// CHECK_SKX_M64: #define __RTM__ 1
 // CHECK_SKX_M64-NOT: #define __SGX__ 1
 // CHECK_SKX_M64: #define __SSE2_MATH__ 1
 // CHECK_SKX_M64: #define __SSE2__ 1
 // CHECK_SKX_M64: #define __SSE3__ 1
 // CHECK_SKX_M64: #define __SSE4_1__ 1
 // CHECK_SKX_M64: #define __SSE4_2__ 1
 // CHECK_SKX_M64: #define __SSE_MATH__ 1
 // CHECK_SKX_M64: #define __SSE__ 1

 // CHECK_CNL_M32: #define __MOVBE__ 1
 // CHECK_CNL_M32: #define __MPX__ 1
 // CHECK_CNL_M32: #define __PCLMUL__ 1
 // CHECK_CNL_M32: #define __PKU__ 1
 // CHECK_CNL_M32: #define __POPCNT__ 1
 // CHECK_CNL_M32: #define __PRFCHW__ 1
 // CHECK_CNL_M32: #define __RDRND__ 1
 // CHECK_CNL_M32: #define __RDSEED__ 1
-// CHECK_CNL_M32: #define __RTM__ 1
 // CHECK_CNL_M32: #define __SGX__ 1
 // CHECK_CNL_M32: #define __SHA__ 1
 // CHECK_CNL_M32: #define __SSE2__ 1
 // CHECK_CNL_M32: #define __SSE3__ 1
 // CHECK_CNL_M32: #define __SSE4_1__ 1
 // CHECK_CNL_M32: #define __SSE4_2__ 1
 // CHECK_CNL_M32: #define __SSE__ 1
 // CHECK_CNL_M32: #define __SSSE3__ 1

 // CHECK_CNL_M64: #define __MOVBE__ 1
 // CHECK_CNL_M64: #define __MPX__ 1
 // CHECK_CNL_M64: #define __PCLMUL__ 1
 // CHECK_CNL_M64: #define __PKU__ 1
 // CHECK_CNL_M64: #define __POPCNT__ 1
 // CHECK_CNL_M64: #define __PRFCHW__ 1
 // CHECK_CNL_M64: #define __RDRND__ 1
 // CHECK_CNL_M64: #define __RDSEED__ 1
-// CHECK_CNL_M64: #define __RTM__ 1
 // CHECK_CNL_M64: #define __SGX__ 1
 // CHECK_CNL_M64: #define __SHA__ 1
 // CHECK_CNL_M64: #define __SSE2__ 1
 // CHECK_CNL_M64: #define __SSE3__ 1
 // CHECK_CNL_M64: #define __SSE4_1__ 1
 // CHECK_CNL_M64: #define __SSE4_2__ 1
 // CHECK_CNL_M64: #define __SSE__ 1
 // CHECK_CNL_M64: #define __SSSE3__ 1

 // CHECK_ICL_M32: #define __MPX__ 1
 // CHECK_ICL_M32: #define __PCLMUL__ 1
 // CHECK_ICL_M32: #define __PKU__ 1
 // CHECK_ICL_M32: #define __POPCNT__ 1
 // CHECK_ICL_M32: #define __PRFCHW__ 1
 // CHECK_ICL_M32: #define __RDPID__ 1
 // CHECK_ICL_M32: #define __RDRND__ 1
 // CHECK_ICL_M32: #define __RDSEED__ 1
-// CHECK_ICL_M32: #define __RTM__ 1
 // CHECK_ICL_M32: #define __SGX__ 1
 // CHECK_ICL_M32: #define __SHA__ 1
 // CHECK_ICL_M32: #define __SSE2__ 1
 // CHECK_ICL_M32: #define __SSE3__ 1
 // CHECK_ICL_M32: #define __SSE4_1__ 1
 // CHECK_ICL_M32: #define __SSE4_2__ 1
 // CHECK_ICL_M32: #define __SSE__ 1
 // CHECK_ICL_M32: #define __SSSE3__ 1

 // CHECK_ICL_M64: #define __MPX__ 1
 // CHECK_ICL_M64: #define __PCLMUL__ 1
 // CHECK_ICL_M64: #define __PKU__ 1
 // CHECK_ICL_M64: #define __POPCNT__ 1
 // CHECK_ICL_M64: #define __PRFCHW__ 1
 // CHECK_ICL_M64: #define __RDPID__ 1
 // CHECK_ICL_M64: #define __RDRND__ 1
 // CHECK_ICL_M64: #define __RDSEED__ 1
-// CHECK_ICL_M64: #define __RTM__ 1
 // CHECK_ICL_M64: #define __SGX__ 1
 // CHECK_ICL_M64: #define __SHA__ 1
 // CHECK_ICL_M64: #define __SSE2__ 1
 // CHECK_ICL_M64: #define __SSE3__ 1
 // CHECK_ICL_M64: #define __SSE4_1__ 1
 // CHECK_ICL_M64: #define __SSE4_2__ 1
 // CHECK_ICL_M64: #define __SSE__ 1
 // CHECK_ICL_M64: #define __SSSE3__ 1

 // CHECK_ICX_M32: #define __PCLMUL__ 1
 // CHECK_ICX_M32: #define __PCONFIG__ 1
 // CHECK_ICX_M32: #define __PKU__ 1
 // CHECK_ICX_M32: #define __POPCNT__ 1
 // CHECK_ICX_M32: #define __PRFCHW__ 1
 // CHECK_ICX_M32: #define __RDPID__ 1
 // CHECK_ICX_M32: #define __RDRND__ 1
 // CHECK_ICX_M32: #define __RDSEED__ 1
-// CHECK_ICX_M32: #define __RTM__ 1
 // CHECK_ICX_M32: #define __SGX__ 1
 // CHECK_ICX_M32: #define __SHA__ 1
 // CHECK_ICX_M32: #define __SSE2__ 1
 // CHECK_ICX_M32: #define __SSE3__ 1
 // CHECK_ICX_M32: #define __SSE4_1__ 1
 // CHECK_ICX_M32: #define __SSE4_2__ 1
 // CHECK_ICX_M32: #define __SSE__ 1
 // CHECK_ICX_M32: #define __SSSE3__ 1

 // CHECK_ICX_M64: #define __PCLMUL__ 1
 // CHECK_ICX_M64: #define __PCONFIG__ 1
 // CHECK_ICX_M64: #define __PKU__ 1
 // CHECK_ICX_M64: #define __POPCNT__ 1
 // CHECK_ICX_M64: #define __PRFCHW__ 1
 // CHECK_ICX_M64: #define __RDPID__ 1
 // CHECK_ICX_M64: #define __RDRND__ 1
 // CHECK_ICX_M64: #define __RDSEED__ 1
-// CHECK_ICX_M64: #define __RTM__ 1
 // CHECK_ICX_M64: #define __SGX__ 1
 // CHECK_ICX_M64: #define __SHA__ 1
 // CHECK_ICX_M64: #define __SSE2__ 1
 // CHECK_ICX_M64: #define __SSE3__ 1
 // CHECK_ICX_M64: #define __SSE4_1__ 1
 // CHECK_ICX_M64: #define __SSE4_2__ 1
 // CHECK_ICX_M64: #define __SSE__ 1
 // CHECK_ICX_M64: #define __SSSE3__ 1