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Differential D52556

Add a test case showing the instcombine fail from D52548
ClosedPublic

Authored by sheredom on Sep 26 2018, 8:19 AM.

Details

Reviewers
spatel
Commits
rG150afce75ae9: [InstCombine] add tests that show undef propagation failures from D52548; NFC
rL343140: [InstCombine] add tests that show undef propagation failures from D52548; NFC
Summary

This is a splice out from D52548 to add the test case that causes the instcombine fail, with the expected output pre-fixing it (notice the 0.0f's suddenly appearing because instcombine thinks it can optimize the div/rems away).

Diff Detail

Event Timeline

sheredom created this revision.Sep 26 2018, 8:19 AM
Herald added a subscriber: llvm-commits. · View Herald TranscriptSep 26 2018, 8:19 AM
spatel added inline comments.Sep 26 2018, 9:17 AM
test/Transforms/InstCombine/stop_bad_undef_propagation.ll
122–123

Here and below: there are spacing glitches, so this doesn't compile.

126

Here and in all tests: do we need fast-math-flags?

130

It's not clear what different problems each of the 3 tests per opcode are demonstrating. Please add a comment at the top of the file or give the tests a meaningful name that describes what is changing between the tests.

sheredom updated this revision to Diff 167162.Sep 26 2018, 10:42 AM
  • Added a comment explaining each of the 3 variants for each of sdiv/srem/udiv/urem
  • Fixed the whitespace issue
  • Removed the FMF flags that were a legacy from the original shader this was reduced form
sheredom marked 3 inline comments as done.Sep 26 2018, 10:43 AM
lebedev.ri mentioned this in D52548: Stop instcombining propagating wider shufflevector arguments to predecessors..Sep 26 2018, 12:35 PM
spatel accepted this revision.Sep 26 2018, 1:22 PM

LGTM - I'll remove the block label to shrink this a bit, give the values real names (makes it easier to mix and match instructions if needed), and commit on your behalf. Thanks!

This revision is now accepted and ready to land.Sep 26 2018, 1:22 PM
spatel added inline comments.Sep 26 2018, 1:26 PM
test/Transforms/InstCombine/stop_bad_undef_propagation.ll
148

Not sure how you're generating this, but it still has at least 3 typos that prevent compilation.

Closed by commit rL343140: [InstCombine] add tests that show undef propagation failures from D52548; NFC (authored by spatel). · Explain WhySep 26 2018, 1:32 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
test/
Transforms/
InstCombine/
218 lines

Diff 167144

test/Transforms/InstCombine/stop_bad_undef_propagation.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
define <3 x float> @udiv0(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @udiv0(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = udiv <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @udiv1(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @udiv1(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = udiv <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @udiv2(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @udiv2(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = udiv <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @sdiv0(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @sdiv0(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = sdiv <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @sdiv1(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @sdiv1(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = sdiv <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @sdiv2(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @sdiv2(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = sdiv <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @urem0(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @urem0(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2= urem <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2to <2 x float>
spatelUnsubmitted
Done
ReplyInline Actions

Here and below: there are spacing glitches, so this doesn't compile.

spatel: Here and below: there are spacing glitches, so this doesn't compile.
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
spatelUnsubmitted
Done
ReplyInline Actions

Here and in all tests: do we need fast-math-flags?

spatel: Here and in all tests: do we need fast-math-flags?
ret <3 x float> %6
}
define <3 x float> @urem1(<3 x float> %x, i32 %y, i32 %z) {
spatelUnsubmitted
Done
ReplyInline Actions

It's not clear what different problems each of the 3 tests per opcode are demonstrating. Please add a comment at the top of the file or give the tests a meaningful name that describes what is changing between the tests.

spatel: It's not clear what different problems each of the 3 tests per opcode are demonstrating. Please…
; CHECK-LABEL: @urem1(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2= urem <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @urem2(<3 x float> %x, i32 %y, i32 %z) {
spatelUnsubmitted
Not Done
ReplyInline Actions

Not sure how you're generating this, but it still has at least 3 typos that prevent compilation.

spatel: Not sure how you're generating this, but it still has at least 3 typos that prevent compilation.
; CHECK-LABEL: @urem2(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2= urem <2 x i32> %1, <i32 255, i32 255>
%3 = uitofp <2 x i32> %2to <2 x float>
%4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @srem0(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @srem0(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = srem <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @srem1(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @srem1(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = srem <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}
define <3 x float> @srem2(<3 x float> %x, i32 %y, i32 %z) {
; CHECK-LABEL: @srem2(
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
; CHECK-NEXT: ret <3 x float> [[TMP1]]
;
.entry:
%0 = insertelement <2 x i32> undef, i32 %y, i32 0
%1 = insertelement <2 x i32> %0, i32 %z, i32 1
%2 = srem <2 x i32> %1, <i32 255, i32 255>
%3 = sitofp <2 x i32> %2 to <2 x float>
%4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
%5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
%6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
ret <3 x float> %6
}