[X86] Fix use SSE registers if no-x87 is selected.

[niravd]

Summary

Fix use of SSE1 registers for f32 ops in no-x87 mode.

Notably, allow use of SSE instructions for f32 operations in 64-bit
mode (but not 32-bit which is disallowed by callign convention).

Also avoid translating memset/memcopy/memmove into SSE registers
without X87 for 32-bit mode.

This fixes PR38738.

[nickdesaulniers]

llvm/lib/Target/X86/X86ISelLowering.cpp

1922–1952 ↗

(On Diff #167142)

This whole block should be guarded from trying to use fp registers if the target does not have x87. The current patch overfits our bizarro test case.

Can you then add test cases for other combinations:
+avx,-x87, size >32 (L1928)
+sse2,-x87 (L1936)
+sse2,-x87,memcpy > 8B, i686 (L1942)

[niravd]

Update tests

[niravd]

Update to better match GCC's behavior. Not as aggressive as we can be.

[niravd]

Fix typo.

[niravd]

llvm/lib/Target/X86/X86ISelLowering.cpp

1922–1952 ↗

(On Diff #167142)

Looking at the history of this more, it seems that HasX87 was meant to correspond to mno-80387 which is disabling use of the x87 coprocessor. Without X87, GCC allows SSE2 (and successors) instructions, but avoids using SSE1 registers for memset. etc.

[niravd]

[nickdesaulniers]

llvm/lib/Target/X86/X86ISelLowering.cpp

282 ↗

(On Diff #167806)

How come not also this case? Or any of the ISD::FP_TO_SINT?

552 ↗

(On Diff #167806)

Below (L1947) you check Subtarget.is64Bit() || Subtarget.hasX87(), so I'm curious here why the additional !useSoftFloat()?

580–590 ↗

(On Diff #167806)

Is it possible to share some of this code with the case starting at L591? Seems to be a fair amount of code duplication. Maybe a helper, or a single case can be checked for these?

[niravd]

Address comments.

[niravd]

llvm/lib/Target/X86/X86ISelLowering.cpp

282 ↗

(On Diff #167806)

Good catch. This looks was a not reverted change from a failed simplification. Reverted

552 ↗

(On Diff #167806)

If we're using SoftFloat we don't want f32/f64 to have an associated register class so we will fall back to the integer registers.

Ideally we'd be able to still use the SSE1 registers for the memory shuffling operations, but that requires more plumbing and GCC doesn't use XMM registers in this case so I've left it off for this.

[nickdesaulniers]

I've tested this patch and it fixes the cases from PR38738, and I'm happy with the code changes. @craig.topper , would you mind reviewing, too?

llvm/lib/Target/X86/X86ISelLowering.cpp

612 ↗

(On Diff #167962)

Testing the raw patch file, looks like this line has trailing whitespace. Did you mean to have a trailing comment, like L603 above?

[craig.topper]

llvm/test/CodeGen/X86/pr38738.ll

12 ↗

(On Diff #167962)

Do we need the dso_local in these tests?

[niravd]

Simplify tests. Add comment.

[nickdesaulniers]

Thank you for this patch, @niravd !

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

for (auto VT : { MVT::f32, MVT::f64 }) {
       setOperationAction(ISD::FCOS   , VT, Expand);
       setOperationAction(ISD::FSINCOS, VT, Expand);
     }
 
     // Lower this to MOVMSK plus an AND.
     setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
     setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
 
-    // Expand FP immediates into loads from the stack, except for the special
-    // cases we handle.
-    addLegalFPImmediate(APFloat(+0.0)); // xorpd
-    addLegalFPImmediate(APFloat(+0.0f)); // xorps
-  } else if (UseX87 && X86ScalarSSEf32) {
+  } else if (!useSoftFloat() && X86ScalarSSEf32 && (UseX87 || Is64Bit)) {
     // Use SSE for f32, x87 for f64.
     // Set up the FP register classes.
     addRegisterClass(MVT::f32, &X86::FR32RegClass);
+    if (UseX87)
       addRegisterClass(MVT::f64, &X86::RFP64RegClass);
 
     // Use ANDPS to simulate FABS.
     setOperationAction(ISD::FABS , MVT::f32, Custom);
 
     // Use XORP to simulate FNEG.
     setOperationAction(ISD::FNEG , MVT::f32, Custom);
 
-    setOperationAction(ISD::UNDEF,     MVT::f64, Expand);
+    if (UseX87)
+      setOperationAction(ISD::UNDEF, MVT::f64, Expand);
 
     // Use ANDPS and ORPS to simulate FCOPYSIGN.
+    if (UseX87)
       setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
 
     // We don't support sin/cos/fmod
     setOperationAction(ISD::FSIN   , MVT::f32, Expand);
     setOperationAction(ISD::FCOS   , MVT::f32, Expand);
     setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
 
-    // Special cases we handle for FP constants.
-    addLegalFPImmediate(APFloat(+0.0f)); // xorps
-    addLegalFPImmediate(APFloat(+0.0)); // FLD0
-    addLegalFPImmediate(APFloat(+1.0)); // FLD1
-    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
-    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
-
+    if (UseX87) {
       // Always expand sin/cos functions even though x87 has an instruction.
-    setOperationAction(ISD::FSIN   , MVT::f64, Expand);
-    setOperationAction(ISD::FCOS   , MVT::f64, Expand);
+      setOperationAction(ISD::FSIN, MVT::f64, Expand);
+      setOperationAction(ISD::FCOS, MVT::f64, Expand);
       setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
+    }
   } else if (UseX87) {
     // f32 and f64 in x87.
     // Set up the FP register classes.
     addRegisterClass(MVT::f64, &X86::RFP64RegClass);
     addRegisterClass(MVT::f32, &X86::RFP32RegClass);
 
     for (auto VT : { MVT::f32, MVT::f64 }) {
       setOperationAction(ISD::UNDEF,     VT, Expand);
       setOperationAction(ISD::FCOPYSIGN, VT, Expand);
 
       // Always expand sin/cos functions even though x87 has an instruction.
       setOperationAction(ISD::FSIN   , VT, Expand);
       setOperationAction(ISD::FCOS   , VT, Expand);
       setOperationAction(ISD::FSINCOS, VT, Expand);
     }
-    addLegalFPImmediate(APFloat(+0.0)); // FLD0
-    addLegalFPImmediate(APFloat(+1.0)); // FLD1
-    addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
-    addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
+  }
+
+  // Expand FP32 immediates into loads from the stack, save special cases.
+  if (isTypeLegal(MVT::f32)) {
+    if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
       addLegalFPImmediate(APFloat(+0.0f)); // FLD0
       addLegalFPImmediate(APFloat(+1.0f)); // FLD1
       addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
       addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
+    } else // SSE immediates.
+      addLegalFPImmediate(APFloat(+0.0f)); // xorps
+  }
+  // Expand FP64 immediates into loads from the stack, save special cases.
+  if (isTypeLegal(MVT::f64)) {
+    if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
+      addLegalFPImmediate(APFloat(+0.0)); // FLD0
+      addLegalFPImmediate(APFloat(+1.0)); // FLD1
+      addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
+      addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
+    } else // SSE immediates.
+      addLegalFPImmediate(APFloat(+0.0)); // xorpd
   }
 
   // We don't support FMA.
   setOperationAction(ISD::FMA, MVT::f64, Expand);
   setOperationAction(ISD::FMA, MVT::f32, Expand);
 
   // Long double always uses X87, except f128 in MMX.
   if (UseX87) {
if (Size >= 16 &&
         // choose an optimal type with a vector element larger than a byte,
         // getMemsetStores() may create an intermediate splat (using an integer
         // multiply) before we splat as a vector.
         return MVT::v32i8;
       }
       if (Subtarget.hasSSE2())
         return MVT::v16i8;
       // TODO: Can SSE1 handle a byte vector?
-      if (Subtarget.hasSSE1())
+      // If we have SSE1 registers we should be able to use them.
+      if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()))
         return MVT::v4f32;
     } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
                !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
       // Do not use f64 to lower memcpy if source is string constant. It's
       // better to use i32 to avoid the loads.
       // Also, do not use f64 to lower memset unless this is a memset of zeros.
       // The gymnastics of splatting a byte value into an XMM register and then
       // only using 8-byte stores (because this is a CPU with slow unaligned

llvm/trunk/test/CodeGen/X86/pr38738.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+sse,-sse2 %s  | FileCheck --check-prefixes=X64SSE %s
+; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+sse,-sse2 %s    | FileCheck --check-prefixes=X86SSE %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+sse2,-sse3 %s | FileCheck --check-prefixes=X64SSE2 %s
+; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+sse2,-sse3 %s   | FileCheck --check-prefixes=X86SSE2 %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+avx,-avx2 %s  | FileCheck --check-prefixes=X64AVX %s
+; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+avx,-avx2 %s    | FileCheck --check-prefixes=X86AVX %s
+
+
+%struct.params = type { double, double }
+
+define i32 @pr38738() {
+; X64SSE-LABEL: pr38738:
+; X64SSE:       # %bb.0: # %entry
+; X64SSE-NEXT:    xorps %xmm0, %xmm0
+; X64SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64SSE-NEXT:    movl $0, -{{[0-9]+}}(%rsp)
+; X64SSE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
+; X64SSE-NEXT:    retq
+;
+; X86SSE-LABEL: pr38738:
+; X86SSE:       # %bb.0: # %entry
+; X86SSE-NEXT:    subl $28, %esp
+; X86SSE-NEXT:    .cfi_def_cfa_offset 32
+; X86SSE-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86SSE-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86SSE-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86SSE-NEXT:    movl $0, (%esp)
+; X86SSE-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE-NEXT:    addl $28, %esp
+; X86SSE-NEXT:    .cfi_def_cfa_offset 4
+; X86SSE-NEXT:    retl
+;
+; X64SSE2-LABEL: pr38738:
+; X64SSE2:       # %bb.0: # %entry
+; X64SSE2-NEXT:    xorps %xmm0, %xmm0
+; X64SSE2-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64SSE2-NEXT:    movl $0, -{{[0-9]+}}(%rsp)
+; X64SSE2-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
+; X64SSE2-NEXT:    retq
+;
+; X86SSE2-LABEL: pr38738:
+; X86SSE2:       # %bb.0: # %entry
+; X86SSE2-NEXT:    subl $44, %esp
+; X86SSE2-NEXT:    .cfi_def_cfa_offset 48
+; X86SSE2-NEXT:    xorps %xmm0, %xmm0
+; X86SSE2-NEXT:    movaps %xmm0, {{[0-9]+}}(%esp)
+; X86SSE2-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE2-NEXT:    addl $44, %esp
+; X86SSE2-NEXT:    .cfi_def_cfa_offset 4
+; X86SSE2-NEXT:    retl
+;
+; X64AVX-LABEL: pr38738:
+; X64AVX:       # %bb.0: # %entry
+; X64AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X64AVX-NEXT:    vmovaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64AVX-NEXT:    movl $0, -{{[0-9]+}}(%rsp)
+; X64AVX-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
+; X64AVX-NEXT:    retq
+;
+; X86AVX-LABEL: pr38738:
+; X86AVX:       # %bb.0: # %entry
+; X86AVX-NEXT:    subl $44, %esp
+; X86AVX-NEXT:    .cfi_def_cfa_offset 48
+; X86AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X86AVX-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%esp)
+; X86AVX-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; X86AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86AVX-NEXT:    addl $44, %esp
+; X86AVX-NEXT:    .cfi_def_cfa_offset 4
+; X86AVX-NEXT:    retl
+entry:
+  %retval = alloca i32, align 4
+  %dlg_sys_param = alloca %struct.params, align 8
+  %total_active_bw = alloca float, align 4
+  %0 = bitcast %struct.params* %dlg_sys_param to i8*
+  call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 16, i1 false)
+  store float 0.000000e+00, float* %total_active_bw, align 4
+  %1 = load i32, i32* %retval, align 4
+  ret i32 %1
+}
+
+define void @tryset(i8* nocapture %x) {
+; X64SSE-LABEL: tryset:
+; X64SSE:       # %bb.0:
+; X64SSE-NEXT:    movq $0, 56(%rdi)
+; X64SSE-NEXT:    movq $0, 48(%rdi)
+; X64SSE-NEXT:    movq $0, 40(%rdi)
+; X64SSE-NEXT:    movq $0, 32(%rdi)
+; X64SSE-NEXT:    movq $0, 24(%rdi)
+; X64SSE-NEXT:    movq $0, 16(%rdi)
+; X64SSE-NEXT:    movq $0, 8(%rdi)
+; X64SSE-NEXT:    movq $0, (%rdi)
+; X64SSE-NEXT:    retq
+;
+; X86SSE-LABEL: tryset:
+; X86SSE:       # %bb.0:
+; X86SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE-NEXT:    movl $0, 60(%eax)
+; X86SSE-NEXT:    movl $0, 56(%eax)
+; X86SSE-NEXT:    movl $0, 52(%eax)
+; X86SSE-NEXT:    movl $0, 48(%eax)
+; X86SSE-NEXT:    movl $0, 44(%eax)
+; X86SSE-NEXT:    movl $0, 40(%eax)
+; X86SSE-NEXT:    movl $0, 36(%eax)
+; X86SSE-NEXT:    movl $0, 32(%eax)
+; X86SSE-NEXT:    movl $0, 28(%eax)
+; X86SSE-NEXT:    movl $0, 24(%eax)
+; X86SSE-NEXT:    movl $0, 20(%eax)
+; X86SSE-NEXT:    movl $0, 16(%eax)
+; X86SSE-NEXT:    movl $0, 12(%eax)
+; X86SSE-NEXT:    movl $0, 8(%eax)
+; X86SSE-NEXT:    movl $0, 4(%eax)
+; X86SSE-NEXT:    movl $0, (%eax)
+; X86SSE-NEXT:    retl
+;
+; X64SSE2-LABEL: tryset:
+; X64SSE2:       # %bb.0:
+; X64SSE2-NEXT:    movq $0, 56(%rdi)
+; X64SSE2-NEXT:    movq $0, 48(%rdi)
+; X64SSE2-NEXT:    movq $0, 40(%rdi)
+; X64SSE2-NEXT:    movq $0, 32(%rdi)
+; X64SSE2-NEXT:    movq $0, 24(%rdi)
+; X64SSE2-NEXT:    movq $0, 16(%rdi)
+; X64SSE2-NEXT:    movq $0, 8(%rdi)
+; X64SSE2-NEXT:    movq $0, (%rdi)
+; X64SSE2-NEXT:    retq
+;
+; X86SSE2-LABEL: tryset:
+; X86SSE2:       # %bb.0:
+; X86SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE2-NEXT:    movl $0, 4(%eax)
+; X86SSE2-NEXT:    movl $0, (%eax)
+; X86SSE2-NEXT:    movl $0, 12(%eax)
+; X86SSE2-NEXT:    movl $0, 8(%eax)
+; X86SSE2-NEXT:    movl $0, 20(%eax)
+; X86SSE2-NEXT:    movl $0, 16(%eax)
+; X86SSE2-NEXT:    movl $0, 28(%eax)
+; X86SSE2-NEXT:    movl $0, 24(%eax)
+; X86SSE2-NEXT:    movl $0, 36(%eax)
+; X86SSE2-NEXT:    movl $0, 32(%eax)
+; X86SSE2-NEXT:    movl $0, 44(%eax)
+; X86SSE2-NEXT:    movl $0, 40(%eax)
+; X86SSE2-NEXT:    movl $0, 52(%eax)
+; X86SSE2-NEXT:    movl $0, 48(%eax)
+; X86SSE2-NEXT:    movl $0, 60(%eax)
+; X86SSE2-NEXT:    movl $0, 56(%eax)
+; X86SSE2-NEXT:    retl
+;
+; X64AVX-LABEL: tryset:
+; X64AVX:       # %bb.0:
+; X64AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X64AVX-NEXT:    vmovups %ymm0, 32(%rdi)
+; X64AVX-NEXT:    vmovups %ymm0, (%rdi)
+; X64AVX-NEXT:    vzeroupper
+; X64AVX-NEXT:    retq
+;
+; X86AVX-LABEL: tryset:
+; X86AVX:       # %bb.0:
+; X86AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X86AVX-NEXT:    vmovups %ymm0, 32(%eax)
+; X86AVX-NEXT:    vmovups %ymm0, (%eax)
+; X86AVX-NEXT:    vzeroupper
+; X86AVX-NEXT:    retl
+  tail call void @llvm.memset.p0i8.i64(i8* align 1 %x, i8 0, i64 64, i1 false)
+  ret void
+}
+
+define void @trycpy(i8* nocapture %x, i8* nocapture readonly %y) {
+; X64SSE-LABEL: trycpy:
+; X64SSE:       # %bb.0:
+; X64SSE-NEXT:    movq 24(%rsi), %rax
+; X64SSE-NEXT:    movq %rax, 24(%rdi)
+; X64SSE-NEXT:    movq 16(%rsi), %rax
+; X64SSE-NEXT:    movq %rax, 16(%rdi)
+; X64SSE-NEXT:    movq (%rsi), %rax
+; X64SSE-NEXT:    movq 8(%rsi), %rcx
+; X64SSE-NEXT:    movq %rcx, 8(%rdi)
+; X64SSE-NEXT:    movq %rax, (%rdi)
+; X64SSE-NEXT:    retq
+;
+; X86SSE-LABEL: trycpy:
+; X86SSE:       # %bb.0:
+; X86SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86SSE-NEXT:    movl 28(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 28(%eax)
+; X86SSE-NEXT:    movl 24(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 24(%eax)
+; X86SSE-NEXT:    movl 20(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 20(%eax)
+; X86SSE-NEXT:    movl 16(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 16(%eax)
+; X86SSE-NEXT:    movl 12(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 12(%eax)
+; X86SSE-NEXT:    movl 8(%ecx), %edx
+; X86SSE-NEXT:    movl %edx, 8(%eax)
+; X86SSE-NEXT:    movl (%ecx), %edx
+; X86SSE-NEXT:    movl 4(%ecx), %ecx
+; X86SSE-NEXT:    movl %ecx, 4(%eax)
+; X86SSE-NEXT:    movl %edx, (%eax)
+; X86SSE-NEXT:    retl
+;
+; X64SSE2-LABEL: trycpy:
+; X64SSE2:       # %bb.0:
+; X64SSE2-NEXT:    movq 24(%rsi), %rax
+; X64SSE2-NEXT:    movq %rax, 24(%rdi)
+; X64SSE2-NEXT:    movq 16(%rsi), %rax
+; X64SSE2-NEXT:    movq %rax, 16(%rdi)
+; X64SSE2-NEXT:    movq (%rsi), %rax
+; X64SSE2-NEXT:    movq 8(%rsi), %rcx
+; X64SSE2-NEXT:    movq %rcx, 8(%rdi)
+; X64SSE2-NEXT:    movq %rax, (%rdi)
+; X64SSE2-NEXT:    retq
+;
+; X86SSE2-LABEL: trycpy:
+; X86SSE2:       # %bb.0:
+; X86SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X86SSE2-NEXT:    movsd %xmm0, 24(%eax)
+; X86SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X86SSE2-NEXT:    movsd %xmm0, 16(%eax)
+; X86SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X86SSE2-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; X86SSE2-NEXT:    movsd %xmm1, 8(%eax)
+; X86SSE2-NEXT:    movsd %xmm0, (%eax)
+; X86SSE2-NEXT:    retl
+;
+; X64AVX-LABEL: trycpy:
+; X64AVX:       # %bb.0:
+; X64AVX-NEXT:    vmovups (%rsi), %ymm0
+; X64AVX-NEXT:    vmovups %ymm0, (%rdi)
+; X64AVX-NEXT:    vzeroupper
+; X64AVX-NEXT:    retq
+;
+; X86AVX-LABEL: trycpy:
+; X86AVX:       # %bb.0:
+; X86AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86AVX-NEXT:    vmovups (%ecx), %ymm0
+; X86AVX-NEXT:    vmovups %ymm0, (%eax)
+; X86AVX-NEXT:    vzeroupper
+; X86AVX-NEXT:    retl
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 32, i1 false)
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #2
+

llvm/trunk/test/CodeGen/X86/x87.ll

-; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefix=X87
-; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse | FileCheck %s -check-prefix=X87
-; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s -check-prefix=NOX87
-; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse | FileCheck %s -check-prefix=NOX87
-; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87
-; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse2 | FileCheck %s -check-prefix=NOX87
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefixes=X8732,X87
+; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse | FileCheck %s -check-prefixes=X8732,X87
+; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s -check-prefixes=NOX8732,NOX87
+; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse | FileCheck %s -check-prefixes=NOX8732,NOX87
+; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse | FileCheck %s -check-prefixes=NOX8732,NOX87
+; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse2 | FileCheck %s -check-prefixes=X8732_SSE,NOX87
 
 define void @test(i32 %i, i64 %l, float* %pf, double* %pd, fp128* %pld) nounwind readnone {
 ; X87-LABEL: test:
 ; NOX87-LABEL: test:
 
 ; NOX87-NOT: {{ }}f{{.*}}
 
 ; X87: fild
-; NOX87: __floatunsisf
+; NOX8732: __floatunsisf
   %tmp = uitofp i32 %i to float
 
-; X87: fild
-; NOX87: __floatdisf
+; X8732: fild
+; NOX8732: __floatdisf
   %tmp1 = sitofp i64 %l to float
 
-; X87: fadd
-; NOX87: __addsf3
+; X8732: fadd
+; NOX8732: __addsf3
   %tmp2 = fadd float %tmp, %tmp1
 
-; X87: fstp
+; X8732: fstp
   store float %tmp2, float* %pf
 
 ; X87: fild
 ; NOX87: __floatunsidf
   %tmp3 = uitofp i32 %i to double
 
 ; X87: fild
 ; NOX87: __floatdidf