[AMDGPU] Fix ds combine with subregs

[kzhuravl]

LGTM

llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

MachineBasicBlock::iterator  SILoadStoreOptimizer::mergeRead2Pair(
 
   const TargetRegisterClass *SuperRC
     = (CI.EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
   unsigned DestReg = MRI->createVirtualRegister(SuperRC);
 
   DebugLoc DL = CI.I->getDebugLoc();
 
   unsigned BaseReg = AddrReg->getReg();
+  unsigned BaseSubReg = AddrReg->getSubReg();
   unsigned BaseRegFlags = 0;
   if (CI.BaseOff) {
     unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
       .addImm(CI.BaseOff);
 
     BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     BaseRegFlags = RegState::Kill;
 
     TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
       .addReg(ImmReg)
-      .addReg(AddrReg->getReg());
+      .addReg(AddrReg->getReg(), 0, BaseSubReg);
+    BaseSubReg = 0;
   }
 
   MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
-                                  .addReg(BaseReg, BaseRegFlags) // addr
-                                  .addImm(NewOffset0)            // offset0
-                                  .addImm(NewOffset1)            // offset1
-                                  .addImm(0)                     // gds
-                                  .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
+                        .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
+                        .addImm(NewOffset0)                        // offset0
+                        .addImm(NewOffset1)                        // offset1
+                        .addImm(0)                                 // gds
 
   (void)Read2;
 
   const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
 
   // Copy to the old destination registers.
   BuildMI(*MBB, CI.Paired, DL, CopyDesc)
       .add(*Dest0) // Copy to same destination including flags and sub reg.
MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
   assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
          (NewOffset0 != NewOffset1) &&
          "Computed offset doesn't fit");
 
   const MCInstrDesc &Write2Desc = TII->get(Opc);
   DebugLoc DL = CI.I->getDebugLoc();
 
   unsigned BaseReg = AddrReg->getReg();
+  unsigned BaseSubReg = AddrReg->getSubReg();
   unsigned BaseRegFlags = 0;
   if (CI.BaseOff) {
     unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
       .addImm(CI.BaseOff);
 
     BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     BaseRegFlags = RegState::Kill;
 
     TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
       .addReg(ImmReg)
-      .addReg(AddrReg->getReg());
+      .addReg(AddrReg->getReg(), 0, BaseSubReg);
+    BaseSubReg = 0;
   }
 
   MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
-                                   .addReg(BaseReg, BaseRegFlags) // addr
-                                   .add(*Data0)                   // data0
-                                   .add(*Data1)                   // data1
-                                   .addImm(NewOffset0)            // offset0
-                                   .addImm(NewOffset1)            // offset1
-                                   .addImm(0)                     // gds
-                                   .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
+                        .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
+                        .add(*Data0)                               // data0
+                        .add(*Data1)                               // data1
+                        .addImm(NewOffset0)                        // offset0
+                        .addImm(NewOffset1)                        // offset1
+                        .addImm(0)                                 // gds
 
   moveInstsAfter(Write2, CI.InstsToMove);
 
   MachineBasicBlock::iterator Next = std::next(CI.I);
   CI.I->eraseFromParent();
   CI.Paired->eraseFromParent();
 
   LLVM_DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');

llvm/trunk/test/CodeGen/AMDGPU/merge-load-store-vreg.mir

 # RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,VI %s
 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
 
 # If there's a base offset, check that SILoadStoreOptimizer creates
 # V_ADD_{I|U}32_e64 for that offset; _e64 uses a vreg for the carry (rather than
 # $vcc, which is used in _e32); this ensures that $vcc is not inadvertently
 # clobbered.
 
-# GCN-LABEL: name: kernel
+# GCN-LABEL: name: ds_combine_base_offset{{$}}
 
 # VI: V_ADD_I32_e64 %6, %0,
 # VI-NEXT: DS_WRITE2_B32 killed %7, %0, %3, 0, 8,
 # VI: V_ADD_I32_e64 %10, %3,
 # VI-NEXT: DS_READ2_B32 killed %11, 0, 8,
 
 # GFX9: V_ADD_U32_e64 %6, %0,
 # GFX9-NEXT: DS_WRITE2_B32_gfx9 killed %7, %0, %3, 0, 8,
 # GFX9: V_ADD_U32_e64 %9, %3,
 # GFX9-NEXT: DS_READ2_B32_gfx9 killed %10, 0, 8,
 
 --- |
   @0 = internal unnamed_addr addrspace(3) global [256 x float] undef, align 4
 
-  define amdgpu_kernel void @kernel() {
+  define amdgpu_kernel void @ds_combine_base_offset() {
+    bb.0:
+      br label %bb2
+
+    bb1:
+      ret void
+
+    bb2:
+      %tmp = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @0, i32 0, i32 0
+      %tmp1 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 8
+      %tmp2 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 16
+      %tmp3 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 24
+      br label %bb1
+    }
+
+  define amdgpu_kernel void @ds_combine_base_offset_subreg() {
+    bb.0:
+      br label %bb2
+
+    bb1:
+      ret void
+
+    bb2:
+      %tmp = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @0, i32 0, i32 0
+      %tmp1 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 8
+      %tmp2 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 16
+      %tmp3 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 24
+      br label %bb1
+    }
+
+  define amdgpu_kernel void @ds_combine_subreg() {
     bb.0:
       br label %bb2
 
     bb1:
       ret void
 
     bb2:
       %tmp = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @0, i32 0, i32 0
       %tmp1 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 8
       %tmp2 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 16
       %tmp3 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 24
       br label %bb1
     }
 ---
-name:            kernel
+name:            ds_combine_base_offset
 body:             |
   bb.0:
     %0:vgpr_32 = IMPLICIT_DEF
     S_BRANCH %bb.2
 
   bb.1:
     S_ENDPGM
 
   bb.2:
     %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0, 0, implicit $exec
     %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
     V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
     DS_WRITE_B32 %0, %0, 1024, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
     %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32 %0, %3, 1056, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
     %4:vgpr_32 = DS_READ_B32 %3, 1088, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
     %5:vgpr_32 = DS_READ_B32 %3, 1120, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
     $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
     S_CBRANCH_VCCNZ %bb.1, implicit $vcc
     S_BRANCH %bb.1
 ...
+
+# GCN-LABEL: name: ds_combine_base_offset_subreg{{$}}
+
+# VI: V_ADD_I32_e64 %6, %0.sub0,
+# VI-NEXT: DS_WRITE2_B32 killed %7, %0.sub0, %3.sub0, 0, 8,
+# VI: V_ADD_I32_e64 %10, %3.sub0,
+# VI-NEXT: DS_READ2_B32 killed %11, 0, 8,
+
+# GFX9: V_ADD_U32_e64 %6, %0.sub0,
+# GFX9-NEXT: DS_WRITE2_B32_gfx9 killed %7, %0.sub0, %3.sub0, 0, 8,
+# GFX9: V_ADD_U32_e64 %9, %3.sub0,
+# GFX9-NEXT: DS_READ2_B32_gfx9 killed %10, 0, 8,
+---
+name:            ds_combine_base_offset_subreg
+body:             |
+  bb.0:
+    %0:vreg_64 = IMPLICIT_DEF
+    S_BRANCH %bb.2
+
+  bb.1:
+    S_ENDPGM
+
+  bb.2:
+    %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
+    %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
+    V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
+    DS_WRITE_B32 %0.sub0, %0.sub0, 1024, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
+    undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+    DS_WRITE_B32 %0.sub0, %3.sub0, 1056, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
+    %4:vgpr_32 = DS_READ_B32 %3.sub0, 1088, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
+    %5:vgpr_32 = DS_READ_B32 %3.sub0, 1120, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
+    $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
+    S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+    S_BRANCH %bb.1
+...
+
+# GCN-LABEL: name: ds_combine_subreg{{$}}
+
+# VI: DS_WRITE2_B32 %0.sub0, %0.sub0, %3.sub0, 0, 8,
+# VI: DS_READ2_B32 %3.sub0, 0, 8,
+
+# GFX9: DS_WRITE2_B32_gfx9 %0.sub0, %0.sub0, %3.sub0, 0, 8,
+# GFX9: DS_READ2_B32_gfx9 %3.sub0, 0, 8,
+---
+name:            ds_combine_subreg
+body:             |
+  bb.0:
+    %0:vreg_64 = IMPLICIT_DEF
+    S_BRANCH %bb.2
+
+  bb.1:
+    S_ENDPGM
+
+  bb.2:
+    %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
+    %2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
+    V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
+    DS_WRITE_B32 %0.sub0, %0.sub0, 0, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
+    undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+    DS_WRITE_B32 %0.sub0, %3.sub0, 32, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
+    %4:vgpr_32 = DS_READ_B32 %3.sub0, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
+    %5:vgpr_32 = DS_READ_B32 %3.sub0, 32, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
+    $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
+    S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+    S_BRANCH %bb.1
+...