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Differential D52355

AMDGPU: Always run AMDGPUAlwaysInline
ClosedPublic

Authored by arsenm on Sep 21 2018, 5:24 AM.

Details

Reviewers
rampitec
Summary

Even if calls are enabled, it still needs to be run
for forcing inline of functions that use LDS.

Diff Detail

Event Timeline

arsenm created this revision.Sep 21 2018, 5:24 AM
Herald added subscribers: eraman, t-tye, tpr and 6 others. · View Herald TranscriptSep 21 2018, 5:24 AM
rampitec accepted this revision.Sep 21 2018, 9:56 AM

LGTM

This revision is now accepted and ready to land.Sep 21 2018, 9:56 AM
arsenm closed this revision.Oct 2 2018, 7:49 PM

r343657

Revision Contents

PathSize
lib/
Target/
AMDGPU/
21 lines
test/
CodeGen/
AMDGPU/
21 lines

Diff 166458

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 598 Lines • ▼ Show 20 Linesvoid AMDGPUPassConfig::addIRPasses() {
// There is no reason to run these. // There is no reason to run these.
disablePass(&StackMapLivenessID); disablePass(&StackMapLivenessID);
disablePass(&FuncletLayoutID); disablePass(&FuncletLayoutID);
disablePass(&PatchableFunctionID); disablePass(&PatchableFunctionID);
addPass(createAtomicExpandPass()); addPass(createAtomicExpandPass());
addPass(createAMDGPULowerIntrinsicsPass()); addPass(createAMDGPULowerIntrinsicsPass());
if (TM.getTargetTriple().getArch() == Triple::r600 ||
!EnableAMDGPUFunctionCalls) {
// Function calls are not supported, so make sure we inline everything. // Function calls are not supported, so make sure we inline everything.
addPass(createAMDGPUAlwaysInlinePass()); addPass(createAMDGPUAlwaysInlinePass());
addPass(createAlwaysInlinerLegacyPass()); addPass(createAlwaysInlinerLegacyPass());
// We need to add the barrier noop pass, otherwise adding the function // We need to add the barrier noop pass, otherwise adding the function
// inlining pass will cause all of the PassConfigs passes to be run // inlining pass will cause all of the PassConfigs passes to be run
// one function at a time, which means if we have a nodule with two // one function at a time, which means if we have a nodule with two
// functions, then we will generate code for the first function // functions, then we will generate code for the first function
// without ever running any passes on the second. // without ever running any passes on the second.
addPass(createBarrierNoopPass()); addPass(createBarrierNoopPass());
}
if (TM.getTargetTriple().getArch() == Triple::amdgcn) { if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
// TODO: May want to move later or split into an early and late one. // TODO: May want to move later or split into an early and late one.
addPass(createAMDGPUCodeGenPreparePass()); addPass(createAMDGPUCodeGenPreparePass());
} }
// Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments. // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
▲ Show 20 Lines • Show All 276 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-function-calls -amdgpu-stress-function-calls < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s
@lds0 = addrspace(3) global i32 undef, align 4
; GCN-NOT: load_lds_simple
define internal i32 @load_lds_simple() {
%load = load i32, i32 addrspace(3)* @lds0, align 4
ret i32 %load
}
; GCN-LABEL: {{^}}kernel:
; GCN: v_mov_b32_e32 [[ADDR:v[0-9]+]], 0
; GCN: ds_read_b32 v{{[0-9]+}}, [[ADDR]]
define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) {
%call = call i32 @load_lds_simple()
store i32 %call, i32 addrspace(1)* %out
ret void
}