[Arm][AsmParser] Restrict register list size for VSTM/VLDM

[LukeCheeseman]

Summary

• The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
• The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
• This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389

[LukeCheeseman]

ping

[DavidSpickett]

Can you include a test for 0 registers? Maybe "{}" gets caught earlier and you get a different error than this is adding, but it'd be nice for completeness.

[LukeCheeseman]

• Adding 0 registers test

[LukeCheeseman]

Committed in r342891

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::VMOVSRR: {
     // Destination registers must be sequential.
     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
     if (Sm1 != Sm + 1)
       return Error(Operands[3]->getStartLoc(),
                    "destination operands must be sequential");
     break;
   }
+  case ARM::VLDMDIA:
+  case ARM::VSTMDIA: {
+    ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
+    auto &RegList = Op.getRegList();
+    if (RegList.size() < 1 || RegList.size() > 16)
+      return Error(Operands[3]->getStartLoc(),
+                   "list of registers must be at least 1 and at most 16");
+    break;
+  }
   }
 
   return false;
 }
 
 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
   switch(Opc) {
   default: llvm_unreachable("unexpected opcode!");

test/MC/ARM/single-precision-fp.s

 @ CHECK-ERRORS-NEXT: vrinta.f64.f64 d9, d8
 @ CHECK-ERRORS: error: instruction requires: double precision VFP
 @ CHECK-ERRORS-NEXT: vrintn.f64 d7, d6
 @ CHECK-ERRORS: error: instruction requires: double precision VFP
 @ CHECK-ERRORS-NEXT: vrintp.f64.f64 d5, d4
 @ CHECK-ERRORS: error: instruction requires: double precision VFP
 @ CHECK-ERRORS-NEXT: vrintm.f64 d3, d2
 
+        vstm r4, {d15-d30}
+        vstm r4, {d15-d31}
+        vstm r4, {s15-s31}
+        vldm r4, {d15-d30}
+        vldm r4, {d15-d31}
+        vldm r4, {s15-s31}
+@ CHECK:  vstmia  r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
+@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
+@ CHECK:  vstmia  r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+@ CHECK:  vldmia  r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
+@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
+@ CHECK:  vldmia  r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+
         @ Double precisionish operations that actually *are* allowed.
         vldr d0, [sp]
         vstr d3, [sp]
         vldm r0, {d0, d1}
         vstm r4, {d3, d4}
         vpush {d6, d7}
         vpop {d8, d9}
         vmov r1, r0, d1