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Differential D51791

AMDGPU: Use GOT PSV since it has an address space now
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Authored by arsenm on Sep 7 2018, 8:15 AM.

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rampitec

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arsenm created this revision.Sep 7 2018, 8:15 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptSep 7 2018, 8:15 AM
rampitec accepted this revision.Sep 7 2018, 12:22 PM

LGTM

This revision is now accepted and ready to land.Sep 7 2018, 12:22 PM
arsenm closed this revision.Sep 9 2018, 7:25 PM

r341768

Revision Contents

PathSize
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
4 lines

Diff 164430

lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,441 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT, SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
SIInstrInfo::MO_GOTPCREL32); SIInstrInfo::MO_GOTPCREL32);
Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext()); Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS); PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
const DataLayout &DataLayout = DAG.getDataLayout(); const DataLayout &DataLayout = DAG.getDataLayout();
unsigned Align = DataLayout.getABITypeAlignment(PtrTy); unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
// FIXME: Use a PseudoSourceValue once those can be assigned an address space. MachinePointerInfo PtrInfo
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy)); = MachinePointerInfo::getGOT(DAG.getMachineFunction());
return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align, return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
MachineMemOperand::MODereferenceable | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
} }
SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
const SDLoc &DL, SDValue V) const { const SDLoc &DL, SDValue V) const {
▲ Show 20 Lines • Show All 4,775 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/global_smrd.ll

; RUN: llc -O2 -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s
; uniform loads ; uniform loads
; CHECK-LABEL: @uniform_load ; CHECK-LABEL: @uniform_load
; CHECK: s_load_dwordx4 ; CHECK: s_load_dwordx4
; CHECK-NOT: flat_load_dword ; CHECK-NOT: flat_load_dword
define amdgpu_kernel void @uniform_load(float addrspace(1)* %arg, [8 x i32], float addrspace(1)* %arg1) { define amdgpu_kernel void @uniform_load(float addrspace(1)* %arg, [8 x i32], float addrspace(1)* %arg1) {
bb: bb:
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @memdep(i32 addrspace(1)* %in, [8 x i32], i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1) {
%val = load i32, i32 addrspace(1)* %in %val = load i32, i32 addrspace(1)* %in
store i32 %val, i32 addrspace(1)* %out1 store i32 %val, i32 addrspace(1)* %out1
ret void ret void
} }
; uniform load from global array ; uniform load from global array
; CHECK-LABEL: @global_array ; CHECK-LABEL: @global_array
; CHECK: s_getpc_b64 [[GET_PC:s\[[0-9]+:[0-9]+\]]] ; CHECK: s_getpc_b64 [[GET_PC:s\[[0-9]+:[0-9]+\]]]
; CHECK: s_load_dwordx2 [[OUT:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0
; CHECK: s_load_dwordx2 [[A_ADDR:s\[[0-9]+:[0-9]+\]]], [[GET_PC]], 0x0 ; CHECK: s_load_dwordx2 [[A_ADDR:s\[[0-9]+:[0-9]+\]]], [[GET_PC]], 0x0
; CHECK: s_load_dwordx2 [[A_ADDR1:s\[[0-9]+:[0-9]+\]]], [[A_ADDR]], 0x0 ; CHECK: s_load_dwordx2 [[A_ADDR1:s\[[0-9]+:[0-9]+\]]], [[A_ADDR]], 0x0
; CHECK: s_load_dword [[SVAL:s[0-9]+]], [[A_ADDR1]], 0x0 ; CHECK: s_load_dword [[SVAL:s[0-9]+]], [[A_ADDR1]], 0x0
; CHECK: s_load_dwordx2 [[OUT:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0
; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]] ; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]] ; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
@A = common local_unnamed_addr addrspace(1) global i32 addrspace(1)* null, align 4 @A = common local_unnamed_addr addrspace(1) global i32 addrspace(1)* null, align 4
define amdgpu_kernel void @global_array(i32 addrspace(1)* nocapture %out) { define amdgpu_kernel void @global_array(i32 addrspace(1)* nocapture %out) {
entry: entry:
%load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
%load1 = load i32, i32 addrspace(1)* %load0, align 4 %load1 = load i32, i32 addrspace(1)* %load0, align 4
Show All 32 Lines