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Differential D51586

[AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32.
ClosedPublic

Authored by alex-t on Sep 3 2018, 4:32 AM.

Details

Reviewers
rampitec
Summary

Fold immediate move as inline constant to the user instruction in case there is a single use.
Code for inlining Src0 and Src1 has the most in common. I did not place common part to the function for the sake of readability.

Tests: CodeGen/AMDGPU - passed
new MIR test added

Diff Detail

Event Timeline

alex-t created this revision.Sep 3 2018, 4:32 AM
Herald added subscribers: eraman, t-tye, tpr and 7 others. · View Herald TranscriptSep 3 2018, 4:32 AM
arsenm added a comment.Sep 3 2018, 8:22 AM

Add another case where the register is physical, I think this will assert as is

lib/Target/AMDGPU/SIInstrInfo.cpp
2071–2073

Comment indentation is wrong

2080–2081

Formatting

2087

Indentation

alex-t updated this revision to Diff 163783.Sep 4 2018, 4:35 AM

Formatting corrected.

alex-t updated this revision to Diff 164154.Sep 6 2018, 12:58 AM
alex-t retitled this revision from [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline move immediate. to [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32..
alex-t marked 3 inline comments as done.

Physical registers handling added. Test cases for physical registers added.

rampitec accepted this revision.Sep 6 2018, 11:47 AM

LGTM

This revision is now accepted and ready to land.Sep 6 2018, 11:47 AM
alex-t closed this revision.Sep 13 2018, 5:52 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
38 lines
test/
CodeGen/
AMDGPU/
185 lines

Diff 164154

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 2,060 Lines • ▼ Show 20 Lines if (Src0->isReg() && Src0->getReg() == Reg) {
return true; return true;
} }
// Added part is the constant: Use v_madak_{f16, f32}. // Added part is the constant: Use v_madak_{f16, f32}.
if (Src2->isReg() && Src2->getReg() == Reg) { if (Src2->isReg() && Src2->getReg() == Reg) {
// Not allowed to use constant bus for another operand. // Not allowed to use constant bus for another operand.
// We can however allow an inline immediate as src0. // We can however allow an inline immediate as src0.
if (!Src0->isImm() && bool Src0Inlined = false;
(Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) if (Src0->isReg()) {
return false; // Try to inline constant if possible.
// If the Def moves immediate and the use is single
if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) // We are saving VGPR here.
arsenmUnsubmitted
Done
ReplyInline Actions

Comment indentation is wrong

arsenm: Comment indentation is wrong
MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
if (Def && Def->isMoveImmediate() &&
isInlineConstant(Def->getOperand(1)) &&
MRI->hasOneUse(Src0->getReg())) {
Src0->ChangeToImmediate(Def->getOperand(1).getImm());
Src0Inlined = true;
} else if ((RI.isPhysicalRegister(Src0->getReg()) &&
RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg()))) ||
arsenmUnsubmitted
Done
ReplyInline Actions

Formatting

arsenm: Formatting
(RI.isVirtualRegister(Src0->getReg()) &&
RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
return false;
// VGPR is okay as Src0 - fallthrough
}
arsenmUnsubmitted
Done
ReplyInline Actions

Indentation

arsenm: Indentation
if (Src1->isReg() && !Src0Inlined ) {
// We have one slot for inlinable constant so far - try to fill it
MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
if (Def && Def->isMoveImmediate() &&
isInlineConstant(Def->getOperand(1)) &&
MRI->hasOneUse(Src1->getReg()) &&
commuteInstruction(UseMI)) {
Src0->ChangeToImmediate(Def->getOperand(1).getImm());
} else if ((RI.isPhysicalRegister(Src1->getReg()) &&
RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
(RI.isVirtualRegister(Src1->getReg()) &&
RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
return false; return false;
// VGPR is okay as Src1 - fallthrough
}
const int64_t Imm = ImmOp->getImm(); const int64_t Imm = ImmOp->getImm();
// FIXME: This would be a lot easier if we could return a new instruction // FIXME: This would be a lot easier if we could return a new instruction
// instead of having to modify in place. // instead of having to modify in place.
// Remove these first since they are at the end. // Remove these first since they are at the end.
UseMI.RemoveOperand( UseMI.RemoveOperand(
▲ Show 20 Lines • Show All 3,184 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/madak-inline-constant.mir

  • This file was added.
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192
# GCN: S_MOV_B32 1082130432
# GCN: %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
---
name: test src1-inlined
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:sreg_32 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192
# GCN: S_MOV_B32 1082130432
# GCN: %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
---
name: test src0-inlined
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:sreg_32 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192
# GCN: S_MOV_B32 1082130432
# GCN: %3:vgpr_32 = V_MADAK_F32 killed %0, killed %0, 1092616192, implicit $exec
---
name: test none-inlined
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:sreg_32 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %0, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192
# GCN: V_MOV_B32_e32 1082130432
# GCN: %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
---
name: test src1-2vgprs-inlined
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec
%19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192
# GCN: V_MOV_B32_e32 1082130432
# GCN: %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
---
name: test src0-2vgprs-inlined
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec
%19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192, implicit $exec
# GCN: S_MOV_B32 1082130432
# GCN: V_MADAK_F32 1082130432, killed $vgpr1, 1092616192, implicit $exec
---
name: test src0-phys-vgpr
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
$vgpr1 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:sgpr_32 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed $vgpr1, 0, killed %18, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192, implicit $exec
# GCN: S_MOV_B32 1082130432
# GCN: V_MADAK_F32 1082130432, killed $vgpr0, 1092616192, implicit $exec
---
name: test src1-phys-vgpr
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%18:sgpr_32 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed $vgpr0, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192, implicit $exec
# GCN: V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %1, 0, 0, implicit $exec
---
name: test src0-phys-sgpr
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%19:vgpr_32 = V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192, implicit $exec
# GCN: V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %1, 0, 0, implicit $exec
---
name: test src1-phys-sgpr
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
%19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $exec
...
# GCN-LABEL: bb.0:
# GCN: V_MOV_B32_e32 1092616192, implicit $exec
# GCN: $sgpr2 = S_MOV_B32 1082130432
# GCN: V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
---
name: test src1-phys-sgpr-move
body: |
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0
%17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
$sgpr2 = S_MOV_B32 1082130432
%19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $exec
...