Don't count debug instructions towards neighborhood count

[arsenm]

Summary

In computeRegisterLiveness, the max instructions to search
was counting dbg_value instructions, which could potentially
cause an observable codegen change from the presence of debug
info.

[MatzeB]

LGTM, thanks

[arsenm]

r341028

lib/CodeGen/MachineBasicBlock.cpp

MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
                                            unsigned Reg, const_iterator Before,
                                            unsigned Neighborhood) const {
   unsigned N = Neighborhood;
 
   // Try searching forwards from Before, looking for reads or defs.
   const_iterator I(Before);
   // If this is the last insn in the block, don't search forwards.
   if (I != end()) {
-    for (++I; I != end() && N > 0; ++I, --N) {
+    for (++I; I != end() && N > 0; ++I) {
+      if (I->isDebugInstr())
+        continue;
+
+      --N;
+
       MachineOperandIteratorBase::PhysRegInfo Info =
           ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
 
       // Register is live when we read it here.
       if (Info.Read)
         return LQR_Live;
       // Register is dead if we can fully overwrite or clobber it here.
       if (Info.FullyDefined || Info.Clobbered)
MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
 
   // Start by searching backwards from Before, looking for kills, reads or defs.
   I = const_iterator(Before);
   // If this is the first insn in the block, don't search backwards.
   if (I != begin()) {
     do {
       --I;
 
+      if (I->isDebugInstr())
+        continue;
+
+      --N;
+
       MachineOperandIteratorBase::PhysRegInfo Info =
           ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
 
       // Defs happen after uses so they take precedence if both are present.
 
       // Register is dead after a dead def of the full register.
       if (Info.DeadDef)
         return LQR_Dead;
       // Register is (at least partially) live after a def.
       if (Info.Defined) {
         if (!Info.PartialDeadDef)
           return LQR_Live;
         // As soon as we saw a partial definition (dead or not),
         // we cannot tell if the value is partial live without
         // tracking the lanemasks. We are not going to do this,
         // so fall back on the remaining of the analysis.
         break;
       }
       // Register is dead after a full kill or clobber and no def.
       if (Info.Killed || Info.Clobbered)
         return LQR_Dead;
       // Register must be live if we read it.
       if (Info.Read)
         return LQR_Live;
-    } while (I != begin() && --N > 0);
+
+    } while (I != begin() && N > 0);
   }
 
   // Did we get to the start of the block?
   if (I == begin()) {
     // If so, the register's state is definitely defined by the live-in state.
     for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); RAI.isValid();
          ++RAI)
       if (isLiveIn(*RAI))
         return LQR_Live;
 
     return LQR_Dead;
   }
 
-
   // At this point we have no idea of the liveness of the register.
   return LQR_Unknown;
 }
 
 const uint32_t *
 MachineBasicBlock::getBeginClobberMask(const TargetRegisterInfo *TRI) const {
   // EH funclet entry does not preserve any registers.
   return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;

test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir

bb.0:
     %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
     S_NOP 0
     S_NOP 0
 
   bb.1:
     S_ENDPGM implicit %2
 
 ...
+---
+
+# This requires searching through many DBG_VALUE instructions before the insert poitn, which
+# should not count against the search limit.
+
+name: vcc_liveness_dbg_value_search_before
+tracksRegLiveness: true
+
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: vcc_liveness_dbg_value_search_before
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    %0:sreg_32_xm0 = S_MOV_B32 12345
+    %1:vgpr_32 = IMPLICIT_DEF
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
+    S_ENDPGM implicit %2
+
+...
+---
+
+# This requires searching through many DBG_VALUE instructions after the insert point, which
+# should not count against the search limit.
+
+name: vcc_liveness_dbg_value_search_after
+tracksRegLiveness: true
+
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: vcc_liveness_dbg_value_search_after
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: DBG_VALUE $noreg, 0
+    ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
+    %0:sreg_32_xm0 = S_MOV_B32 12345
+    %1:vgpr_32 = IMPLICIT_DEF
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    DBG_VALUE $noreg, 0
+    $vcc = S_MOV_B64 0
+    S_ENDPGM implicit %2
+
+...