[PowerPC][MC] Support expressions in getMemRIX16Encoding

[sfertile]

Summary

Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like lxv 3, global@toc@l(3)

[nemanjai]

Other than the minor nit about the test case, this LGTM.

test/MC/PowerPC/ppc64-dq-expr.s

1 ↗

(On Diff #162029)

This may be silly as I'm not familiar with similar tests, but won't you require the -f option to force the binary output to stdout?

[sfertile]

test/MC/PowerPC/ppc64-dq-expr.s

1 ↗

(On Diff #162029)

Not a silly question since that's the behavior I expected as well, but llvm-mc is happy to output binary to the term without -f. I just realized after committing this that I probably don't even need -o - since outputting to the term seems to be the default anyway.

llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
   // displacement and the next 5 bits as the register #.
   assert(MI.getOperand(OpNo+1).isReg());
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
 
   const MCOperand &MO = MI.getOperand(OpNo);
-  assert(MO.isImm() && !(MO.getImm() % 16) &&
+  if (MO.isImm()) {
+    assert(!(MO.getImm() % 16) &&
            "Expecting an immediate that is a multiple of 16");
-
     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
   }
 
+  // Otherwise add a fixup for the displacement field.
+  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
+                                   (MCFixupKind)PPC::fixup_ppc_half16ds));
+  return RegBits;
+}
+
 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
                                               SmallVectorImpl<MCFixup> &Fixups,
                                               const MCSubtargetInfo &STI)
                                               const {
   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
   // as the displacement and the next 5 bits as the register #.
   assert(MI.getOperand(OpNo+1).isReg());
   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;

llvm/trunk/test/MC/PowerPC/ppc64-dq-expr.s

+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu %s -filetype=obj -o - | \
+# RUN:    llvm-objdump -D  -r - | FileCheck %s
+        .text
+        .abiversion 2
+        .global test
+        .p2align 4
+        .type test,@function
+test:
+.Lgep:
+        addis 2, 12, .TOC.-.Lgep@ha
+        addi  2,  2, .TOC.-.Lgep@l
+.Llep:
+        .localentry  test, .Llep-.Lgep
+        addis 3, 2, vecA@toc@ha
+        lxv   3,    vecA@toc@l(3)
+        addis 3, 2, vecB@toc@ha
+        stxv  3,    vecB@toc@l(3)
+        blr
+
+        .comm  vecA, 16, 16
+        .comm  vecB, 16, 16
+
+# CHECK: Disassembly of section .text:
+# CHECK-LABEL: test:
+# CHECK-NEXT:    addis 2, 12, 0
+# CHECK-NEXT:    R_PPC64_REL16_HA     .TOC.
+# CHECK-NEXT:    addi 2, 2, 0
+# CHECK-NEXT:    R_PPC64_REL16_LO     .TOC.
+# CHECK-NEXT:    addis 3, 2, 0
+# CHECK-NEXT:    R_PPC64_TOC16_HA     vecA
+# CHECK-NEXT:    lxv 3, 0(3)
+# CHECK-NEXT:    R_PPC64_TOC16_LO_DS  vecA
+# CHECK-NEXT:    addis 3, 2, 0
+# CHECK-NEXT:    R_PPC64_TOC16_HA     vecB
+# CHECK-NEXT:    stxv 3, 0(3)
+# CHECK-NEXT:    R_PPC64_TOC16_LO_DS  vecB
+# CHECK-NEXT:    blr
+