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Differential D50553

[X86] Add constant folding for AVX512 versions of scalar floating point to integer conversion intrinsics.
ClosedPublic

Authored by craig.topper on Aug 9 2018, 11:47 PM.

Details

Reviewers
RKSimon
spatel
chandlerc
Commits
rG484b342c68ab: [X86] Add constant folding for AVX512 versions of scalar floating point to…
rL339529: [X86] Add constant folding for AVX512 versions of scalar floating point to…
Summary

We've supported constant folding for sse versions for many years. This patch adds support for the avx512 versions including unsigned with the default rounding mode. We could probably do more with other roundings modes and SAE in the future.

The test cases are largely based on the sse.ll test cases. But I did add some test cases to ensure the unsigned versions don't accept negative values. Also checked the bounds of f64->i32 conversions to make sure unsigned has a larger positive range than signed.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Aug 9 2018, 11:47 PM
Harbormaster completed remote builds in B21317: Diff 160064.Aug 9 2018, 11:47 PM
craig.topper updated this revision to Diff 160065.Aug 9 2018, 11:55 PM

Add FIXME for other rounding modes

Harbormaster completed remote builds in B21318: Diff 160065.Aug 9 2018, 11:55 PM
RKSimon accepted this revision.Aug 12 2018, 6:38 AM

LGTM

This revision is now accepted and ready to land.Aug 12 2018, 6:38 AM
Closed by commit rL339529: [X86] Add constant folding for AVX512 versions of scalar floating point to… (authored by ctopper). · Explain WhyAug 12 2018, 3:10 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Analysis/
81 lines
test/
Transforms/
ConstProp/
490 lines

Diff 160276

llvm/trunk/lib/Analysis/ConstantFolding.cpp

Show First 20 Lines • Show All 1,407 Lines • ▼ Show 20 Linesbool llvm::canConstantFoldCallTo(ImmutableCallSite CS, const Function *F) {
case Intrinsic::x86_sse_cvtss2si: case Intrinsic::x86_sse_cvtss2si:
case Intrinsic::x86_sse_cvtss2si64: case Intrinsic::x86_sse_cvtss2si64:
case Intrinsic::x86_sse_cvttss2si: case Intrinsic::x86_sse_cvttss2si:
case Intrinsic::x86_sse_cvttss2si64: case Intrinsic::x86_sse_cvttss2si64:
case Intrinsic::x86_sse2_cvtsd2si: case Intrinsic::x86_sse2_cvtsd2si:
case Intrinsic::x86_sse2_cvtsd2si64: case Intrinsic::x86_sse2_cvtsd2si64:
case Intrinsic::x86_sse2_cvttsd2si: case Intrinsic::x86_sse2_cvttsd2si:
case Intrinsic::x86_sse2_cvttsd2si64: case Intrinsic::x86_sse2_cvttsd2si64:
case Intrinsic::x86_avx512_vcvtss2si32:
case Intrinsic::x86_avx512_vcvtss2si64:
case Intrinsic::x86_avx512_cvttss2si:
case Intrinsic::x86_avx512_cvttss2si64:
case Intrinsic::x86_avx512_vcvtsd2si32:
case Intrinsic::x86_avx512_vcvtsd2si64:
case Intrinsic::x86_avx512_cvttsd2si:
case Intrinsic::x86_avx512_cvttsd2si64:
case Intrinsic::x86_avx512_vcvtss2usi32:
case Intrinsic::x86_avx512_vcvtss2usi64:
case Intrinsic::x86_avx512_cvttss2usi:
case Intrinsic::x86_avx512_cvttss2usi64:
case Intrinsic::x86_avx512_vcvtsd2usi32:
case Intrinsic::x86_avx512_vcvtsd2usi64:
case Intrinsic::x86_avx512_cvttsd2usi:
case Intrinsic::x86_avx512_cvttsd2usi64:
return true; return true;
default: default:
return false; return false;
case Intrinsic::not_intrinsic: break; case Intrinsic::not_intrinsic: break;
} }
if (!F->hasName()) if (!F->hasName())
return false; return false;
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
/// Attempt to fold an SSE floating point to integer conversion of a constant /// Attempt to fold an SSE floating point to integer conversion of a constant
/// floating point. If roundTowardZero is false, the default IEEE rounding is /// floating point. If roundTowardZero is false, the default IEEE rounding is
/// used (toward nearest, ties to even). This matches the behavior of the /// used (toward nearest, ties to even). This matches the behavior of the
/// non-truncating SSE instructions in the default rounding mode. The desired /// non-truncating SSE instructions in the default rounding mode. The desired
/// integer type Ty is used to select how many bits are available for the /// integer type Ty is used to select how many bits are available for the
/// result. Returns null if the conversion cannot be performed, otherwise /// result. Returns null if the conversion cannot be performed, otherwise
/// returns the Constant value resulting from the conversion. /// returns the Constant value resulting from the conversion.
Constant *ConstantFoldSSEConvertToInt(const APFloat &Val, bool roundTowardZero, Constant *ConstantFoldSSEConvertToInt(const APFloat &Val, bool roundTowardZero,
Type *Ty) { Type *Ty, bool IsSigned) {
// All of these conversion intrinsics form an integer of at most 64bits. // All of these conversion intrinsics form an integer of at most 64bits.
unsigned ResultWidth = Ty->getIntegerBitWidth(); unsigned ResultWidth = Ty->getIntegerBitWidth();
assert(ResultWidth <= 64 && assert(ResultWidth <= 64 &&
"Can only constant fold conversions to 64 and 32 bit ints"); "Can only constant fold conversions to 64 and 32 bit ints");
uint64_t UIntVal; uint64_t UIntVal;
bool isExact = false; bool isExact = false;
APFloat::roundingMode mode = roundTowardZero? APFloat::rmTowardZero APFloat::roundingMode mode = roundTowardZero? APFloat::rmTowardZero
: APFloat::rmNearestTiesToEven; : APFloat::rmNearestTiesToEven;
APFloat::opStatus status = APFloat::opStatus status =
Val.convertToInteger(makeMutableArrayRef(UIntVal), ResultWidth, Val.convertToInteger(makeMutableArrayRef(UIntVal), ResultWidth,
/*isSigned=*/true, mode, &isExact); IsSigned, mode, &isExact);
if (status != APFloat::opOK && if (status != APFloat::opOK &&
(!roundTowardZero || status != APFloat::opInexact)) (!roundTowardZero || status != APFloat::opInexact))
return nullptr; return nullptr;
return ConstantInt::get(Ty, UIntVal, /*isSigned=*/true); return ConstantInt::get(Ty, UIntVal, IsSigned);
} }
double getValueAsDouble(ConstantFP *Op) { double getValueAsDouble(ConstantFP *Op) {
Type *Ty = Op->getType(); Type *Ty = Op->getType();
if (Ty->isFloatTy()) if (Ty->isFloatTy())
return Op->getValueAPF().convertToFloat(); return Op->getValueAPF().convertToFloat();
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines if (isa<ConstantVector>(Operands[0]) ||
default: break; default: break;
case Intrinsic::x86_sse_cvtss2si: case Intrinsic::x86_sse_cvtss2si:
case Intrinsic::x86_sse_cvtss2si64: case Intrinsic::x86_sse_cvtss2si64:
case Intrinsic::x86_sse2_cvtsd2si: case Intrinsic::x86_sse2_cvtsd2si:
case Intrinsic::x86_sse2_cvtsd2si64: case Intrinsic::x86_sse2_cvtsd2si64:
if (ConstantFP *FPOp = if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U))) dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(), return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/false, Ty); /*roundTowardZero=*/false, Ty,
/*IsSigned*/true);
break; break;
case Intrinsic::x86_sse_cvttss2si: case Intrinsic::x86_sse_cvttss2si:
case Intrinsic::x86_sse_cvttss2si64: case Intrinsic::x86_sse_cvttss2si64:
case Intrinsic::x86_sse2_cvttsd2si: case Intrinsic::x86_sse2_cvttsd2si:
case Intrinsic::x86_sse2_cvttsd2si64: case Intrinsic::x86_sse2_cvttsd2si64:
if (ConstantFP *FPOp = if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U))) dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(), return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/true, Ty); /*roundTowardZero=*/true, Ty,
/*IsSigned*/true);
break; break;
} }
} }
return nullptr; return nullptr;
} }
if (Operands.size() == 2) { if (Operands.size() == 2) {
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines if (auto *Op1 = dyn_cast<ConstantInt>(Operands[0])) {
if (Op2->isOne() && Op1->isZero()) // ctlz(0, 1) is undef. if (Op2->isOne() && Op1->isZero()) // ctlz(0, 1) is undef.
return UndefValue::get(Ty); return UndefValue::get(Ty);
return ConstantInt::get(Ty, Op1->getValue().countLeadingZeros()); return ConstantInt::get(Ty, Op1->getValue().countLeadingZeros());
} }
} }
return nullptr; return nullptr;
} }
// Support ConstantVector in case we have an Undef in the top.
if ((isa<ConstantVector>(Operands[0]) ||
isa<ConstantDataVector>(Operands[0])) &&
// Check for default rounding mode.
// FIXME: Support other rounding modes?
isa<ConstantInt>(Operands[1]) &&
cast<ConstantInt>(Operands[1])->getValue() == 4) {
auto *Op = cast<Constant>(Operands[0]);
switch (IntrinsicID) {
default: break;
case Intrinsic::x86_avx512_vcvtss2si32:
case Intrinsic::x86_avx512_vcvtss2si64:
case Intrinsic::x86_avx512_vcvtsd2si32:
case Intrinsic::x86_avx512_vcvtsd2si64:
if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/false, Ty,
/*IsSigned*/true);
break;
case Intrinsic::x86_avx512_vcvtss2usi32:
case Intrinsic::x86_avx512_vcvtss2usi64:
case Intrinsic::x86_avx512_vcvtsd2usi32:
case Intrinsic::x86_avx512_vcvtsd2usi64:
if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/false, Ty,
/*IsSigned*/false);
break;
case Intrinsic::x86_avx512_cvttss2si:
case Intrinsic::x86_avx512_cvttss2si64:
case Intrinsic::x86_avx512_cvttsd2si:
case Intrinsic::x86_avx512_cvttsd2si64:
if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/true, Ty,
/*IsSigned*/true);
break;
case Intrinsic::x86_avx512_cvttss2usi:
case Intrinsic::x86_avx512_cvttss2usi64:
case Intrinsic::x86_avx512_cvttsd2usi:
case Intrinsic::x86_avx512_cvttsd2usi64:
if (ConstantFP *FPOp =
dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))
return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),
/*roundTowardZero=*/true, Ty,
/*IsSigned*/false);
break;
}
}
return nullptr; return nullptr;
} }
if (Operands.size() != 3) if (Operands.size() != 3)
return nullptr; return nullptr;
if (const auto *Op1 = dyn_cast<ConstantFP>(Operands[0])) { if (const auto *Op1 = dyn_cast<ConstantFP>(Operands[0])) {
if (const auto *Op2 = dyn_cast<ConstantFP>(Operands[1])) { if (const auto *Op2 = dyn_cast<ConstantFP>(Operands[1])) {
▲ Show 20 Lines • Show All 269 Lines • Show Last 20 Lines

llvm/trunk/test/Transforms/ConstProp/avx512.ll

; RUN: opt < %s -constprop -S | FileCheck %s
; REQUIRES: x86-registered-target
define i1 @test_avx512_cvts_exact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_exact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 10
%cmp13 = icmp eq i64 %sum13, 10
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
define i1 @test_avx512_cvts_exact_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_exact_max(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double 2147483647.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, 2147483647
ret i1 %b
}
define i1 @test_avx512_cvts_exact_max_p1() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_exact_max_p1(
; CHECK: call
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double 2147483648.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, 2147483648
ret i1 %b
}
define i1 @test_avx512_cvts_exact_neg_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_exact_neg_max(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double -2147483648.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, -2147483648
ret i1 %b
}
define i1 @test_avx512_cvts_exact_neg_max_p1() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_exact_neg_max_p1(
; CHECK: call
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double -2147483649.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, -2147483649
ret i1 %b
}
; Inexact values should not fold as they are dependent on rounding mode
define i1 @test_avx512_cvts_inexact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_inexact(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 4
%cmp13 = icmp eq i64 %sum13, 4
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
; FLT_MAX/DBL_MAX should not fold
define i1 @test_avx512_cvts_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_max(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095039, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405311, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; INF should not fold
define i1 @test_avx512_cvts_inf() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_inf(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095040, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405312, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; NAN should not fold
define i1 @test_avx512_cvts_nan() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvts_nan(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2143289344, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9221120237041090560, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
define i1 @test_avx512_cvtts_exact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtts_exact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 10
%cmp13 = icmp eq i64 %sum13, 10
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
define i1 @test_avx512_cvtts_inexact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtts_inexact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 2
%cmp13 = icmp eq i64 %sum13, 2
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
; FLT_MAX/DBL_MAX should not fold
define i1 @test_avx512_cvtts_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtts_max(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095039, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405311, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; INF should not fold
define i1 @test_avx512_cvtts_inf() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtts_inf(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095040, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405312, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; NAN should not fold
define i1 @test_avx512_cvtts_nan() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtts_nan(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2143289344, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9221120237041090560, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
define i1 @test_avx512_cvtu_exact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_exact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 10
%cmp13 = icmp eq i64 %sum13, 10
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
; Negative values should not fold as they can't be represented in an unsigned int.
define i1 @test_avx512_cvtu_neg() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_neg(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> <float -3.0, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> <float -3.0, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> <double -7.0, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> <double -7.0, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, -10
%cmp13 = icmp eq i64 %sum13, -10
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
define i1 @test_avx512_cvtu_exact_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_exact_max(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> <double 4294967295.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, 4294967295
ret i1 %b
}
define i1 @test_avx512_cvtu_exact_max_p1() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_exact_max_p1(
; CHECK: call
entry:
%i0 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> <double 4294967296.0, double undef>, i32 4) nounwind
%b = icmp eq i32 %i0, 4294967296
ret i1 %b
}
; Inexact values should not fold as they are dependent on rounding mode
define i1 @test_avx512_cvtu_inexact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_inexact(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 4
%cmp13 = icmp eq i64 %sum13, 4
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
; FLT_MAX/DBL_MAX should not fold
define i1 @test_avx512_cvtu_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_max(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095039, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405311, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; INF should not fold
define i1 @test_avx512_cvtu_inf() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_inf(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095040, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405312, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; NAN should not fold
define i1 @test_avx512_cvtu_nan() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvtu_nan(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2143289344, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9221120237041090560, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
define i1 @test_avx512_cvttu_exact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvttu_exact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> <float 3.0, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> <double 7.0, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 10
%cmp13 = icmp eq i64 %sum13, 10
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
define i1 @test_avx512_cvttu_inexact() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvttu_inexact(
; CHECK-NOT: call
; CHECK: ret i1 true
entry:
%i0 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> <float 1.75, float undef, float undef, float undef>, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> <double 1.75, double undef>, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%cmp02 = icmp eq i32 %sum02, 2
%cmp13 = icmp eq i64 %sum13, 2
%b = and i1 %cmp02, %cmp13
ret i1 %b
}
; FLT_MAX/DBL_MAX should not fold
define i1 @test_avx512_cvttu_max() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvttu_max(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095039, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405311, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; INF should not fold
define i1 @test_avx512_cvttu_inf() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvttu_inf(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2139095040, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9218868437227405312, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
; NAN should not fold
define i1 @test_avx512_cvttu_nan() nounwind readnone {
; CHECK-LABEL: @test_avx512_cvttu_nan(
; CHECK: call
; CHECK: call
; CHECK: call
; CHECK: call
entry:
%fm = bitcast <4 x i32> <i32 2143289344, i32 undef, i32 undef, i32 undef> to <4 x float>
%dm = bitcast <2 x i64> <i64 9221120237041090560, i64 undef> to <2 x double>
%i0 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %fm, i32 4) nounwind
%i1 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> %fm, i32 4) nounwind
%i2 = call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %dm, i32 4) nounwind
%i3 = call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> %dm, i32 4) nounwind
%sum02 = add i32 %i0, %i2
%sum13 = add i64 %i1, %i3
%sum02.sext = sext i32 %sum02 to i64
%b = icmp eq i64 %sum02.sext, %sum13
ret i1 %b
}
declare i32 @llvm.x86.avx512.vcvtss2si32(<4 x float>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.cvttss2si(<4 x float>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.vcvtss2si64(<4 x float>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.cvttss2si64(<4 x float>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.cvttsd2si(<2 x double>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.cvttsd2si64(<2 x double>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.cvttss2usi(<4 x float>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.cvttss2usi64(<4 x float>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double>, i32) nounwind readnone
declare i32 @llvm.x86.avx512.cvttsd2usi(<2 x double>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double>, i32) nounwind readnone
declare i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double>, i32) nounwind readnone