This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c.
This is a very first step towards adding PIC support for Linux in the RISC-V backend.
The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses
For now, this patch only introduces support of that pseudo instruction at the assembler parser.
As part of the remaining PIC changes and to avoid code duplication between the codegen flow and the assembler flow, I plan to lower PC-rel addressing (the one that does not use the GOT, e.g. loading a file-scope static variable) into a PseudoLLA. But this means the expansion of the pseudo-instruction still has to happen elsewhere for the codegen flow. Again to avoid code duplication, my idea was to introduce a RISCVELFStreamer which knows how to expand the pseudo-MC-instruction when generating an object (I'm a bit worried though that I might be tying this to ELF). I'd do a similar thing with la (but that will require some more stuff not in upstream yet).
I considered using MCCodeEmitter as we do now for PseudoCALL and PseudoTAIL but I don't think this can work as I need to emit a label, something that the MCCodeEmitter doesn't seem (to the best of my knowledge) able to do.
Hope my plan above makes sense.