AArch64 - Narrow arguments passed in wrong position on the stack in big-endian mode (aarch64_pcs)

[rmaprath]

Summary

Consider the following snippet:

int f(
      long x0, long x1, long x2, long x3,
      long x4, long x5, long x6, long x7,
      char c, short s
      ) {
  return c + s;
}

int g() {
  return f(0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
}

When compiled with: --target=aarch64-none-eabi -mbig-endian -O2 -fno-inline -S

The following assembly is produced:

f:                                      // @f
        ;...
	ldrb	w8, [sp, #4] ; @@@ should be '#7'
	ldrsh	w9, [sp, #12] ; @@@ should be '#14'
        ;...
g:                                      // @g
        ; ...
	strh	w8, [sp, #12] ; @@@ should be '#14'
	strb	w9, [sp, #4] ; @@@ should be '#7'
	bl	f
        ; ...

The actual argument positions on the stack should be as in the comments (as per aarch64_pcs - C14, C15). The attached patch fixes this issue.

[t.p.northover]

Hi Asiri,

This looks fine to me. Do you need someone to commit it for you?

Cheers.

Tim.

[rmaprath]

Thanks Tim!

Amara agreed to commit the patch.

• Asiri

[t.p.northover]

Excellent! Well, thanks for writing it!

Tim.

[aemerson]

Closed by commit rL215716 (authored by @aemerson).

lib/Target/AArch64/AArch64ISelLowering.cpp

     } else { // VA.isRegLoc()
       assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
       unsigned ArgOffset = VA.getLocMemOffset();
-      unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
+      unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
 
       uint32_t BEAlign = 0;
       if (ArgSize < 8 && !Subtarget->isLittleEndian())

       // common case. It should also work for fundamental types too.
       uint32_t BEAlign = 0;
       unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
-                                        : VA.getLocVT().getSizeInBits();
+                                        : VA.getValVT().getSizeInBits();
       OpSize = (OpSize + 7) / 8;
       if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
         if (OpSize < 8)

test/CodeGen/AArch64/arm64-aapcs-be.ll

+; RUN: llc -mtriple=aarch64_be-none-eabi -fast-isel=false < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64_be-none-eabi -fast-isel=true < %s | FileCheck %s
+
+; Check narrow argument passing via stack - callee end
+define i32 @test_narrow_args_callee(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, i8 %c, i16 %s) #0 {
+entry:
+  %conv = zext i8 %c to i32
+  %conv1 = sext i16 %s to i32
+  %add = add nsw i32 %conv1, %conv
+; CHECK-LABEL: test_narrow_args_callee:
+; CHECK-DAG: ldrb w{{[0-9]}}, [sp, #7]
+; CHECK-DAG: ldr{{s?}}h w{{[0-9]}}, [sp, #14]
+  ret i32 %add
+}
+
+; Check narrow argument passing via stack - caller end
+define i32 @test_narrow_args_caller() #0 {
+entry:
+  %call = tail call i32 @test_narrow_args_callee(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9)
+; CHECK-LABEL: test_narrow_args_caller:
+; CHECK-DAG: strh w{{[0-9]}}, [sp, #14]
+; CHECK-DAG: strb w{{[0-9]}}, [sp, #7]
+  ret i32 %call
+}
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