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Differential D49047

[InstCombine] fix shuffle-of-binops transform to avoid poison/undef
ClosedPublic

Authored by spatel on Jul 6 2018, 3:20 PM.

Details

Reviewers
nlopes
lebedev.ri
aqjune
efriedma
spatel
Commits
rG5bd36644c815: [InstCombine] fix shuffle-of-binops transform to avoid poison/undef
rL336546: [InstCombine] fix shuffle-of-binops transform to avoid poison/undef
Summary

As noted in D48987, there are many different ways for this transform to go wrong. In particular, the poison potential for shifts means we have to more careful with those ops. I added tests to make that behavior visible for all of the different cases that I could find.

This is a partial fix. To make this review easier, I did not make changes for the single binop pattern (handled in foldSelectShuffleWith1Binop()). I also left out some potential optimizations noted with TODO comments. I'll follow-up once we're confident that things are correct here.

The goal is to correct all marked FIXME tests (assuming I identified those correctly) to either avoid the shuffle transform or do it safely.

Note that distinguishing when the shuffle mask contains undefs and using getBinOpIdentity() allows for some improvements to div/rem patterns, so there are wins along with the missed opportunities and fixes.

Diff Detail

Event Timeline

spatel created this revision.Jul 6 2018, 3:20 PM
Herald added a subscriber: mcrosier. · View Herald TranscriptJul 6 2018, 3:20 PM
spatel mentioned this in D48987: [InstCombine] drop poison flags for shuffle transforms with undefs.Jul 6 2018, 3:36 PM
spatel mentioned this in D48893: [Constants, InstCombine] allow RHS (operand 1) identity constants for binops.Jul 6 2018, 3:40 PM
nlopes added a comment.Jul 8 2018, 11:10 AM

LGTM.

BTW, I couldn't figure if this case is possible, but mentioning it just in case: it's also not legal to introduce 'sdiv undef, ..', since 'sdiv INT_MIN, -1' is UB. Same for srem. So we need to be careful when folding the shuffle on LHS as well.

spatel added a comment.Jul 9 2018, 6:22 AM
In D49047#1155252, @nlopes wrote:

LGTM.

BTW, I couldn't figure if this case is possible, but mentioning it just in case: it's also not legal to introduce 'sdiv undef, ..', since 'sdiv INT_MIN, -1' is UB. Same for srem. So we need to be careful when folding the shuffle on LHS as well.

Good point - it's not possible for now because we bail out on a LHS constant for div/rem for both patterns (1 variable operand or 2).

spatel accepted this revision.Jul 9 2018, 6:23 AM

(marking as accepted here in Phab to avoid unknown state with the commit)

This revision is now accepted and ready to land.Jul 9 2018, 6:23 AM
Closed by commit rL336546: [InstCombine] fix shuffle-of-binops transform to avoid poison/undef (authored by spatel). · Explain WhyJul 9 2018, 6:26 AM
This revision was automatically updated to reflect the committed changes.
spatel mentioned this in rL336562: [InstCombine] avoid extra poison when moving shift above shuffle.Jul 9 2018, 10:25 AM
spatel mentioned this in rL343727: [InstCombine] allow SimplifyDemandedVectorElts to work with FP binops.Oct 3 2018, 2:48 PM
spatel mentioned this in rL343819: [InstCombine] drop poison flags in SimplifyVectorDemandedElts.Oct 4 2018, 2:40 PM

Revision Contents

PathSize
lib/
Transforms/
InstCombine/
73 lines
test/
Transforms/
InstCombine/
105 lines

Diff 154463

lib/Transforms/InstCombine/InstCombineVectorOps.cpp

Show First 20 Lines • Show All 1,274 Lines • ▼ Show 20 Linesstatic Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf,
} }
if (Opc0 != Opc1) if (Opc0 != Opc1)
return nullptr; return nullptr;
// The opcodes must be the same. Use a new name to make that clear. // The opcodes must be the same. Use a new name to make that clear.
BinaryOperator::BinaryOps BOpc = Opc0; BinaryOperator::BinaryOps BOpc = Opc0;
// We are moving a binop after a shuffle. When a shuffle has an undefined
// mask element, the result is undefined, but it is not poison or undefined
// behavior. That is not necessarily true for div/rem/shift.
Constant *Mask = Shuf.getMask();
bool MightCreatePoisonOrUB =
Mask->containsUndefElement() &&
(Instruction::isIntDivRem(BOpc) || Instruction::isShift(BOpc));
Constant *NewC;
Value *V; Value *V;
if (X == Y) { if (X == Y) {
NewC = ConstantExpr::getShuffleVector(C0, C1, Mask);
// The new binop constant must not have any potential for extra poison/UB.
if (MightCreatePoisonOrUB) {
// TODO: Use getBinOpAbsorber for LHS replacement constants?
if (!ConstantsAreOp1)
return nullptr;
Type *EltTy = Shuf.getType()->getVectorElementType();
auto *IdC = ConstantExpr::getBinOpIdentity(BOpc, EltTy, true);
if (!IdC)
return nullptr;
// Replace undef elements caused by the mask with identity constants.
NewC = ConstantExpr::getShuffleVector(C0, C1, Mask);
unsigned NumElts = Shuf.getType()->getVectorNumElements();
SmallVector<Constant *, 16> VectorOfNewC(NumElts);
for (unsigned i = 0; i != NumElts; i++) {
if (isa<UndefValue>(Mask->getAggregateElement(i)))
VectorOfNewC[i] = IdC;
else
VectorOfNewC[i] = NewC->getAggregateElement(i);
}
NewC = ConstantVector::get(VectorOfNewC);
}
// Remove a binop and the shuffle by rearranging the constant: // Remove a binop and the shuffle by rearranging the constant:
// shuffle (op V, C0), (op V, C1), M --> op V, C' // shuffle (op V, C0), (op V, C1), M --> op V, C'
// shuffle (op C0, V), (op C1, V), M --> op C', V // shuffle (op C0, V), (op C1, V), M --> op C', V
V = X; V = X;
} else if (!Instruction::isIntDivRem(BOpc) && } else {
(B0->hasOneUse() || B1->hasOneUse())) {
// If there are 2 different variable operands, we must create a new shuffle // If there are 2 different variable operands, we must create a new shuffle
// (select) first, so check uses to ensure that we don't end up with more // (select) first, so check uses to ensure that we don't end up with more
// instructions than we started with. // instructions than we started with.
// if (!B0->hasOneUse() && !B1->hasOneUse())
return nullptr;
// Bail out if we can not guarantee safety of the transform.
// TODO: We could try harder by replacing the undef mask elements.
if (MightCreatePoisonOrUB)
return nullptr;
// Note: In general, we do not create new shuffles in InstCombine because we // Note: In general, we do not create new shuffles in InstCombine because we
// do not know if a target can lower an arbitrary shuffle optimally. In this // do not know if a target can lower an arbitrary shuffle optimally. In this
// case, the shuffle uses the existing mask, so there is no additional risk. // case, the shuffle uses the existing mask, so there is no additional risk.
//
// TODO: We are disallowing div/rem because a shuffle with an undef mask
// element would propagate an undef value to the div/rem. That's not
// safe in general because div/rem allow for undefined behavior. We can
// loosen this restriction (eg, check if the mask has no undefs or replace
// undef elements).
// Select the variable vectors first, then perform the binop: // Select the variable vectors first, then perform the binop:
// shuffle (op X, C0), (op Y, C1), M --> op (shuffle X, Y, M), C' // shuffle (op X, C0), (op Y, C1), M --> op (shuffle X, Y, M), C'
// shuffle (op C0, X), (op C1, Y), M --> op C', (shuffle X, Y, M) // shuffle (op C0, X), (op C1, Y), M --> op C', (shuffle X, Y, M)
V = Builder.CreateShuffleVector(X, Y, Shuf.getMask()); NewC = ConstantExpr::getShuffleVector(C0, C1, Mask);
} else { V = Builder.CreateShuffleVector(X, Y, Mask);
return nullptr;
} }
Constant *NewC = ConstantExpr::getShuffleVector(C0, C1, Shuf.getMask());
// If the shuffle mask contains undef elements, then the new constant
// vector will have undefs in those lanes. This could cause the entire
// binop to be undef.
if (Instruction::isIntDivRem(BOpc))
NewC = getSafeVectorConstantForIntDivRem(NewC);
Instruction *NewBO = ConstantsAreOp1 ? BinaryOperator::Create(BOpc, V, NewC) : Instruction *NewBO = ConstantsAreOp1 ? BinaryOperator::Create(BOpc, V, NewC) :
BinaryOperator::Create(BOpc, NewC, V); BinaryOperator::Create(BOpc, NewC, V);
// Flags are intersected from the 2 source binops. // Flags are intersected from the 2 source binops. But there are 2 exceptions:
// 1. If we changed an opcode, poison conditions might have changed.
// 2. If the shuffle had undef mask elements, the new binop might have undefs
// where the original code did not. Drop all poison potential to be safe.
NewBO->copyIRFlags(B0); NewBO->copyIRFlags(B0);
NewBO->andIRFlags(B1); NewBO->andIRFlags(B1);
if (DropNSW) if (DropNSW)
NewBO->setHasNoSignedWrap(false); NewBO->setHasNoSignedWrap(false);
if (Mask->containsUndefElement())
NewBO->dropPoisonGeneratingFlags();
return NewBO; return NewBO;
} }
Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) { Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
Value *LHS = SVI.getOperand(0); Value *LHS = SVI.getOperand(0);
Value *RHS = SVI.getOperand(1); Value *RHS = SVI.getOperand(1);
SmallVector<int, 16> Mask = SVI.getShuffleMask(); SmallVector<int, 16> Mask = SVI.getShuffleMask();
Type *Int32Ty = Type::getInt32Ty(SVI.getContext()); Type *Int32Ty = Type::getInt32Ty(SVI.getContext());
▲ Show 20 Lines • Show All 351 Lines • Show Last 20 Lines

test/Transforms/InstCombine/shuffle_select.ll

Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Poison flags must be dropped or undef must be replaced with safe constant. ; Poison flags must be dropped or undef must be replaced with safe constant.
define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_nsw_undef_mask_elt( ; CHECK-LABEL: @add_add_nsw_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8> ; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 undef, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
Show All 27 Lines
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Poison flags must be dropped or undef must be replaced with safe constant. ; Poison flags must be dropped or undef must be replaced with safe constant.
define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_nuw_undef_mask_elt( ; CHECK-LABEL: @sub_sub_nuw_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = sub nuw <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
Show All 30 Lines
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Shift by undef is poison. Undef must be replaced by safe constant. ; Shift by undef is poison. Undef must be replaced by safe constant.
define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_undef_mask_elt( ; CHECK-LABEL: @shl_shl_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 undef> ; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Shift by undef is poison. Undef must be replaced by safe constant. ; Shift by undef is poison. Undef must be replaced by safe constant.
; TODO: We could have propagated 'nuw' here.
define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_nuw_undef_mask_elt( ; CHECK-LABEL: @shl_shl_nuw_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 undef> ; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: 'exact' could have propagated.
define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_exact_undef_mask_elt( ; CHECK-LABEL: @sdiv_sdiv_exact_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1> ; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8> %t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
define <4 x i32> @urem_urem(<4 x i32> %v0) { define <4 x i32> @urem_urem(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem( ; CHECK-LABEL: @urem_urem(
; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]] ; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: This could be folded by using a safe constant.
define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem_undef_mask_elt( ; CHECK-LABEL: @urem_urem_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 1>, [[V0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
define <4 x i32> @srem_srem(<4 x i32> %v0) { define <4 x i32> @srem_srem(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem( ; CHECK-LABEL: @srem_srem(
; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: This could be folded by using a safe constant.
define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) { define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem_undef_mask_elt( ; CHECK-LABEL: @srem_srem_undef_mask_elt(
; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 1, i32 7, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 undef, i32 6, i32 3>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0 %t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 6, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 6, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Poison flags must be dropped or undef must be replaced with safe constant. ; Poison flags must be dropped or undef must be replaced with safe constant.
define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_nsw_undef_mask_elt( ; CHECK-LABEL: @sub_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
; CHECK-NEXT: [[T3:%.*]] = sub nsw <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]] ; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Poison flags must be dropped or undef must be replaced with safe constant. ; Poison flags must be dropped or undef must be replaced with safe constant.
define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_nuw_undef_mask_elt( ; CHECK-LABEL: @mul_2_vars_nuw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8> ; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Shift by undef is poison. Undef must be replaced by safe constant. ; TODO: Shift by undef is poison. Undef must be replaced by safe constant.
define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_undef_mask_elt( ; CHECK-LABEL: @shl_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> ; CHECK-NEXT: [[T1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 undef, i32 6, i32 3, i32 undef> ; CHECK-NEXT: [[T2:%.*]] = shl <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8>
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: Shift by undef is poison. Undef must be replaced by safe constant. ; TODO: Shift by undef is poison. Undef must be replaced by safe constant.
define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_nsw_undef_mask_elt( ; CHECK-LABEL: @shl_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> ; CHECK-NEXT: [[T1:%.*]] = shl nsw <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 undef, i32 6, i32 3, i32 undef> ; CHECK-NEXT: [[T2:%.*]] = shl nsw <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8>
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: This is not safe for the same reason that div/rem with undef mask is not safe. ; TODO: This could be transformed by using a safe constant.
; Analysis could determine that the shift has an undef shift amount creating poison.
define <4 x i32> @lshr_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @lshr_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars_undef_mask_elt( ; CHECK-LABEL: @lshr_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7> ; CHECK-NEXT: [[T1:%.*]] = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 undef, i32 6, i32 3, i32 8>, [[TMP1]] ; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; FIXME: This is not safe for the same reason that div/rem with undef mask is not safe. ; TODO: This could be transformed by using a safe constant.
; Analysis could determine that the shift has an undef shift amount creating poison.
; The 'exact' could also result in poison by choosing a -1 shift value.
define <4 x i32> @lshr_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @lshr_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars_exact_undef_mask_elt( ; CHECK-LABEL: @lshr_2_vars_exact_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7> ; CHECK-NEXT: [[T1:%.*]] = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T3:%.*]] = lshr exact <4 x i32> <i32 undef, i32 6, i32 3, i32 8>, [[TMP1]] ; CHECK-NEXT: [[T2:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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call void @use_v4i32(<4 x i32> %t2) call void @use_v4i32(<4 x i32> %t2)
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; Div/rem need special handling if the shuffle has undef elements. ; Div/rem need special handling if the shuffle has undef elements.
define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars( ; CHECK-LABEL: @udiv_2_vars(
; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]] ; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
define <4 x i32> @udiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @udiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars_exact( ; CHECK-LABEL: @udiv_2_vars_exact(
; CHECK-NEXT: [[T1:%.*]] = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
; CHECK-NEXT: [[T2:%.*]] = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]] ; CHECK-NEXT: [[T3:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 4, i32 1, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: This could be transformed using a safe constant.
define <4 x i32> @udiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @udiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars_undef_mask_elt( ; CHECK-LABEL: @udiv_2_vars_undef_mask_elt(
; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]] ; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7> ; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: This could be transformed using a safe constant.
define <4 x i32> @udiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @udiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars_exact_undef_mask_elt( ; CHECK-LABEL: @udiv_2_vars_exact_undef_mask_elt(
; CHECK-NEXT: [[T1:%.*]] = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]] ; CHECK-NEXT: [[T2:%.*]] = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7> ; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: If the shuffle has no undefs, it's safe to shuffle the variables first. ; If the shuffle has no undefs, it's safe to shuffle the variables first.
define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars( ; CHECK-LABEL: @sdiv_2_vars(
; CHECK-NEXT: [[T1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
; CHECK-NEXT: [[T2:%.*]] = sdiv <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8> ; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_exact( ; CHECK-LABEL: @sdiv_2_vars_exact(
; CHECK-NEXT: [[T1:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
; CHECK-NEXT: [[T2:%.*]] = sdiv exact <4 x i32> [[V1:%.*]], <i32 5, i32 6, i32 7, i32 8> ; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4> %t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8> %t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
; TODO: If the shuffle has no undefs, it's safe to shuffle the variables first. ; If the shuffle has no undefs, it's safe to shuffle the variables first.
define <4 x i32> @urem_2_vars(<4 x i32> %v0, <4 x i32> %v1) { define <4 x i32> @urem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @urem_2_vars( ; CHECK-LABEL: @urem_2_vars(
; CHECK-NEXT: [[T1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: [[T2:%.*]] = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V1:%.*]] ; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i32> [[T1]], <4 x i32> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x i32> [[T3]] ; CHECK-NEXT: ret <4 x i32> [[T3]]
; ;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0 %t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1 %t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
%t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7> %t3 = shufflevector <4 x i32> %t1, <4 x i32> %t2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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