X86: add alias for pushfw/popfw in Intel mode

[t.p.northover]

Summary

A while ago we changed pushf and popf in Intel mode to generate pushfq and popfq. Unfortunately that left us with no way to get the 16-bit encoding in Intel mode so this patch adds pushfw and popfw as aliases there.

An alternative would be to revert that change (& make sure both are accessible). The reasoning behind the change was discussed a bit in https://bugs.llvm.org/show_bug.cgi?id=32035 and seems to have been motivated primarily by GCC compatiblity (nasm is the same, masm appears to be the opposite).

Technically, I suspect the Intel & AMD manuals would disagree with the status-quo:

+ They don't mention pushfw at all, which would now be the only way to get the 16-bit instruction.
+ The table part of the descriptions says pushf is 16-bit (and pushfq is 64-bit).
+ Conversely the description talks of 64-bits being the default, but in terms of opcode prefixes rather than mnemonics so I'm not sure how much weight it has.
+ The 32-bit paragraph seems to allow multiple variants.

But GCC compatibility is a pretty compelling counter-argument for me, which is why I'm suggesting this fix for the situation.

[t.p.northover]

Ping.

[Gerolf]

+ David, Zia

[craig.topper]

What would happen if we just changed the string on PUSHF16/POPF16 to print pushfw/popfw in Intel syntax?

[craig.topper]

Err. Nevermind i was looking at the AT&T section of applyMnemonicAlias. I think this is fine.

[t.p.northover]

Thanks. Finally got round to committing this as r344949.

llvm/lib/Target/X86/X86InstrInfo.td

 def : MnemonicAlias<"pop",   "popw",  "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"pop",   "popl",  "att">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"pop",   "popq",  "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popf",  "popfw", "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"popf",  "popfl", "att">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"popf",  "popfq", "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popf",  "popfq", "intel">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popfd", "popfl", "att">;
+def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In32BitMode]>;
+def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In64BitMode]>;
 
 // FIXME: This is wrong for "push reg".  "push %bx" should turn into pushw in
 // all modes.  However: "push (addr)" and "push $42" should default to
 // pushl/pushq depending on the current mode.  Similar for "pop %bx"
 def : MnemonicAlias<"push",   "pushw",  "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"push",   "pushl",  "att">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"push",   "pushq",  "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushf",  "pushfw", "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"pushf",  "pushfl", "att">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"pushf",  "pushfq", "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushf",  "pushfq", "intel">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushfd", "pushfl", "att">;
+def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In32BitMode]>;
+def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In64BitMode]>;
 
 def : MnemonicAlias<"popad",  "popal",  "intel">, Requires<[Not64BitMode]>;
 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
 def : MnemonicAlias<"popa",   "popaw",  "intel">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"pusha",  "pushaw", "intel">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"popa",   "popal",  "intel">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"pusha",  "pushal", "intel">, Requires<[In32BitMode]>;
 

llvm/test/MC/X86/intel-syntax-encoding.s

 // CHECK: encoding: [0xf3]
 // CHECK: encoding: [0xf0,0x48,0x01,0x00]
 
 // CHECK: encoding: [0x9c]
 // CHECK: encoding: [0x9d]
 pushf
 popf
 
+// CHECK: encoding: [0x66,0x9c]
+// CHECK: encoding: [0x66,0x9d]
+pushfw
+popfw
+
 LBB0_3:
 // CHECK: encoding: [0xeb,A]
   jmp LBB0_3
 // CHECK: encoding: [0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff]
         movsd   XMM5, QWORD PTR [-8]
 
 // CHECK: encoding: [0xd1,0xe7]
   shl EDI, 1