[X86] When have BMI2, prefer shifts to clear low/high bits, rather than variable mask.

[lebedev.ri]

Summary

This adds a reverse transform for the instcombine canonicalizations
that were added in D47980, D47981.

As discussed later, that was worse at least for the code size,
and potentially for the performance, too.

https://rise4fun.com/Alive/Zmpl

[lebedev.ri]

This is always good re instruction count.
This is good for Ryzen: https://godbolt.org/g/bd6xLh
But e.g. for Haswell, IPC halves, and RThroughput slightly decreases: https://godbolt.org/g/2gUzfP
So i'm not sure, maybe some more guards are needed?

[craig.topper]

Is it possible to reverse this as a DAG combine? I'd rather not produce 2 instructions from one pattern if we can avoid it.

[lebedev.ri]

In D48768#1148439, @craig.topper wrote:

Is it possible to reverse this as a DAG combine? I'd rather not produce 2 instructions from one pattern if we can avoid it.

Probably? I will take a look.
It will still need to produce two instructions (which is safe, since there is one-use check on the mask).

[craig.topper]

If you do the one use check in the DAG combine to qualify the reverse, then we can use existing isel patterns to select each shift individually right?

[lebedev.ri]

In D48768#1148450, @craig.topper wrote:

If you do the one use check in the DAG combine to qualify the reverse, then we can use existing isel patterns to select each shift individually right?

I'm not sure i understand the question.
I would expect that the DAG combine reverse would fully replace these
X86InstrCompiler.td changes, while keeping the same test output.

[craig.topper]

That's what i meant. I think I didn't understand this statement "It will still need to produce two instructions (which is safe, since there is one-use check on the mask)."

[lebedev.ri]

• Rebased ontop of more tests.
• Make it DAGCombine transform, instead of X86InstrCompiler.td
• Add preferShiftsToClearExtremeBits() Target Lowering Hook, defaults to false.
• X86: preferShiftsToClearExtremeBits() - true if BMI2 and 32/64 bit width.
• This exposed one more missing BZHI patternmatch (@f64_bzhi in llvm/test/CodeGen/X86/replace-load-and-with-bzhi.ll started failing.)

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

4797

You may not want to do this for i64 on 32-bit targets. Would that improve the results in clear_highbits64_c0 for example?

lib/Target/X86/X86InstrInfo.td

2566 ↗

(On Diff #153620)

The fact that you needed this patterns is actually a bug in the code that turn turns load+and into the bzhi pattern. Normally the trunc would have narrowed the subtract to 32-bits. But the trunc, shift, and subtract were created after legalize ops, but the shit amount was created as i64. It should have been created directly as an i8. The re-legalize we run as part of the last DAG combine caught it and fixed it, but it was too late to get the subtract fixed.

I suppose this pattern might be useful if the subtract had other users that weren't the truncate which would prevent the normal combine from kicking in. But by that logic we would need to replicate all patterns that all look for truncated subtracts. And it wouldn't be limited to just the BZHI64 patterns. You could have a 32 bit data, but a shift amount that is initially 64 bits.

[craig.topper]

lib/Target/X86/X86InstrInfo.td

2566 ↗

(On Diff #153620)

I've fixed the bad shift creation in r336051

[lebedev.ri]

As suggested, restrict transform of 64-bit case to 64-bit targets.

[lebedev.ri]

Respond to rL336051.

[lebedev.ri]

Any further comments?

[spatel]

I think the original motivating question was independent of any BMI extensions? Ie, which of these is better for a generic x86(-64):

0000000000000000	movl	%esi, %ecx
0000000000000002	shll	%cl, %edi
0000000000000004	movl	%edi, %eax
0000000000000006	shrl	%cl, %eax
0000000000000008	retq

0000000000000000	movl	$0xffffffff, %eax
0000000000000005	movl	%esi, %ecx
0000000000000007	shrl	%cl, %eax
0000000000000009	andl	%edi, %eax
000000000000000b	retq

The 'and' version is bigger and might be slower, so that's not a good default for x86 codegen?

Either way, I think it would be better to change the check-prefixes in the test files so they map to the enabled/disabled target attributes. It's not clear to me that we want to tie the transform to any particular set of those attributes.

[lebedev.ri]

• Rebased ontop of more tests
• Always transform for x86, unless vector, or 64-bit width non-64-bit target.

[spatel]

This implements what was suggested. The BMI2 case looks like a win because it can save an instruction. I'm still not sure about the base case. @craig.topper or @RKSimon probably have a better sense for how that compares on various uarch. We could argue that this patch is just restoring the previous behavior, so that's the least risky and preferred way to go.

[reames]

I may be missing something but isn't this a pessimization for the case where the mask is an immediate that can be directly encoded into the and instruction? Why should we prefer dual shifts over something like an AND RAX, 0xfff?

[craig.topper]

This specifically looks for (and (shl -1, X), Y) or (and (shr -1, X), Y). If Y in either of those is a constant, I think we would have rewritten the LHS side of the shift already and removed the 'and' entirely.

[lebedev.ri]

In D48768#1152526, @reames wrote:

I may be missing something but isn't this a pessimization for the case where the mask is an immediate that can be directly encoded into the and instruction? Why should we prefer dual shifts over something like an AND RAX, 0xfff?

Correct, i'm pretty sure we do not want to pessimize constant masks.

This is looking for a pattern like: x & (-1 << y)
That is, an And, with one side being a shift.
If y is constant, the pattern is x & (-1 << C),
and i'm somewhat expecting that (-1 << C) will be constant-folded into a constant.
So we shouldn't be able to match that.

[reames]

In D48768#1152532, @craig.topper wrote:

This specifically looks for (and (shl -1, X), Y) or (and (shr -1, X), Y). If Y in either of those is a constant, I think we would have rewritten the LHS side of the shift already and removed the 'and' entirely.

That was indeed what I was missing. Thanks for the clarification.

[lebedev.ri]

Ping?

[spatel]

This looks like the right default for x86 based on size of the code and opportunities for other combines (and as noted, it's what we would have produced anyway until very recently), so LGTM.

include/llvm/CodeGen/TargetLowering.h

515

I don't think this line ("Different targets...") adds anything, so I'd remove it.

516

Clearer to say: "Return true if the variant with 2 shifts is preferred."

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4197–4206

It's a matter of taste, but I find it more readable/less code to use if+else or ?: for 2-case logic.

[lebedev.ri]

In D48768#1155724, @spatel wrote:

This looks like the right default for x86 based on size of the code and opportunities for other combines (and as noted, it's what we would have produced anyway until very recently), so LGTM.

Thank you for the review!

[lebedev.ri]

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4193–4194 ↗

(On Diff #154673)

Hmm, this effectively killed test coverage for this pattern for BZHI/BEXTR..
It wouldn't be too much of a problem to just match the expanded pattern there,
but we only unfold if the mask is one-use..

include/llvm/CodeGen/TargetLowering.h

public:
   /// X = ~A & B
   /// This can be used to simplify select or other instructions.
   virtual bool hasAndNot(SDValue X) const {
     // If the target has the more complex version of this operation, assume that
     // it has this operation too.
     return hasAndNotCompare(X);
   }
 
+  /// There are two ways to clear extreme bits (either low or high):
+  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)
+  /// Shifts:  x >> y << y
+  /// Different targets may have different preferences.
+  /// Returns true if the shift variant is preferred.
+  virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
+    // By default, let's assume that everyone prefers masking.
+    return false;
+  }
+
   /// Return true if the target wants to use the optimization that
   /// turns ext(promotableInst1(...(promotableInstN(load)))) into
   /// promotedInst1(...(promotedInstN(ext(load)))).
   bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
 
   /// Return true if the target can combine store(extractelement VectorTy,
   /// Idx).
   /// \p Cost[out] gives the cost of that transformation when this is true.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
                              SDValue N2, SDValue N3, ISD::CondCode CC,
                              bool NotExtCompare = false);
     SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
                                    SDValue N2, SDValue N3, ISD::CondCode CC);
     SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
                               const SDLoc &DL);
     SDValue unfoldMaskedMerge(SDNode *N);
+    SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
     SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
                           const SDLoc &DL, bool foldBooleans);
     SDValue rebuildSetCC(SDValue N);
 
     bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
                            SDValue &CC) const;
     bool isOneUseSetCC(SDValue N) const;
 
for (auto *Load : Loads) {
       CombineTo(Load, NewLoad, NewLoad.getValue(1));
     }
     DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
     return true;
   }
   return false;
 }
 
+// Unfold
+//    x &  (-1 'logical shift' y)
+// To
+//    (x 'opposite logical shift' y) 'logical shift' y
+// if it is better for performance.
+SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
+  assert(N->getOpcode() == ISD::AND);
+
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  // Do we actually prefer shifts over mask?
+  if (!TLI.preferShiftsToClearExtremeBits(N0))
+    return SDValue();
+
+  // Try to match  (-1 '[outer] logical shift' y)
+  unsigned OuterShift;
+  unsigned InnerShift; // The opposite direction to the OuterShift.
+  SDValue Y;           // Shift amount.
+  auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
+    if (!M.hasOneUse())
+      return false;
+    switch (OuterShift = M->getOpcode()) {
+    case ISD::SHL:
+      InnerShift = ISD::SRL;
+      break;
+    case ISD::SRL:
+      InnerShift = ISD::SHL;
+      break;
+    default:
+      return false;
+    }
+    if (!isAllOnesConstant(M->getOperand(0)))
+      return false;
+    Y = M->getOperand(1);
+    return true;
+  };
+
+  SDValue X;
+  if (matchMask(N1))
+    X = N0;
+  else if (matchMask(N0))
+    X = N1;
+  else
+    return SDValue();
+
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
+
+  //     tmp = x   'opposite logical shift' y
+  SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
+  //     ret = tmp 'logical shift' y
+  SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
+
+  return T1;
+}
+
 SDValue DAGCombiner::visitAND(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N1.getValueType();
 
   // x & x --> x
   if (N0 == N1)
     return N0;
SDValue DAGCombiner::visitAND(SDNode *N) {
   }
   // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
   if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
     if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
                                            N0.getOperand(1), false))
       return BSwap;
   }
 
+  if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
+    return Shifts;
+
   return SDValue();
 }
 
 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
                                         bool DemandHighBits) {
   if (!LegalOperations)
     return SDValue();

lib/Target/X86/X86ISelLowering.h

public:
     }
 
     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
 
     bool hasAndNotCompare(SDValue Y) const override;
 
     bool hasAndNot(SDValue Y) const override;
 
+    bool preferShiftsToClearExtremeBits(SDValue Y) const override;
+
     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
       return VT.isScalarInteger();
     }
 
     /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
     MVT hasFastEqualityCompare(unsigned NumBits) const override;
 
     /// Allow multiple load pairs per block for smaller and faster code.

lib/Target/X86/X86ISelLowering.cpp

if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
     return false;
 
   if (VT == MVT::v4i32)
     return true;
 
   return Subtarget.hasSSE2();
 }
 
+bool X86TargetLowering::preferShiftsToClearExtremeBits(SDValue Y) const {
+  EVT VT = Y.getValueType();
+
+  // For vectors, we don't have a preference, but we probably want a mask.
+  if (VT.isVector())
+    return false;
+
+  // We want BMI2's SHLX/SHRX Shifts Without Affecting Flags.
+  if (!Subtarget.hasBMI2())
+    return false;
+
+  // There are only 32-bit and 64-bit forms for SHLX/SHRX.
+  // And 64-bit form is only preferred on 64-bit targets.
+  return (VT == MVT::i32 || (VT == MVT::i64 && Subtarget.is64Bit()));
+}
+
 MVT X86TargetLowering::hasFastEqualityCompare(unsigned NumBits) const {
   MVT VT = MVT::getIntegerVT(NumBits);
   if (isTypeLegal(VT))
     return VT;
 
   // PMOVMSKB can handle this.
   if (NumBits == 128 && isTypeLegal(MVT::v16i8))
     return MVT::v16i8;

test/CodeGen/X86/clear-highbits.ll

 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_highbits32_c0:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shlxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shrxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_highbits32_c0:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits32_c0:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shlxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shrxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = lshr i32 -1, %numhighbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_highbits32_c1_indexzext(i32 %val, i8 %numhighbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_highbits32_c1_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_highbits32_c1_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shlxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shrxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_highbits32_c1_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits32_c1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shlxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shrxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %sh_prom = zext i8 %numhighbits to i32
   %mask = lshr i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_highbits32_c2_load(i32* %w, i32 %numhighbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_highbits32_c2_load:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_highbits32_c2_load:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shrxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-TRANSFORM-NEXT:    shlxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shrxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_highbits32_c2_load:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits32_c2_load:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shlxl %esi, (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    shrxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %mask = lshr i32 -1, %numhighbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_highbits32_c3_load_indexzext(i32* %w, i8 %numhighbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_highbits32_c3_load_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_highbits32_c3_load_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shrxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-TRANSFORM-NEXT:    shlxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shrxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_highbits32_c3_load_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits32_c3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shlxl %esi, (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    shrxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %sh_prom = zext i8 %numhighbits to i32
   %mask = lshr i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_highbits32_c4_commutative(i32 %val, i32 %numhighbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_highbits32_c4_commutative:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_highbits32_c4_commutative:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shlxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shrxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_highbits32_c4_commutative:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrl %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits32_c4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shlxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shrxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = lshr i32 -1, %numhighbits
   %masked = and i32 %val, %mask ; swapped order
   ret i32 %masked
 }
 
 ; 64-bit
 

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits64_c0:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shlxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shrxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = lshr i64 -1, %numhighbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_highbits64_c1_indexzext(i64 %val, i8 %numhighbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_highbits64_c1_indexzext:

 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits64_c1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shlxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shrxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %sh_prom = zext i8 %numhighbits to i64
   %mask = lshr i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_highbits64_c2_load(i64* %w, i64 %numhighbits) nounwind {

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits64_c2_load:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shlxq %rsi, (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    shrxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %mask = lshr i64 -1, %numhighbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_highbits64_c3_load_indexzext(i64* %w, i8 %numhighbits) nounwind {

 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits64_c3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shlxq %rsi, (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    shrxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %sh_prom = zext i8 %numhighbits to i64
   %mask = lshr i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shrq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_highbits64_c4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shlxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shrxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = lshr i64 -1, %numhighbits
   %masked = and i64 %val, %mask ; swapped order
   ret i64 %masked
 }
 
 ; ---------------------------------------------------------------------------- ;
 ; Multi-use tests

test/CodeGen/X86/clear-lowbits.ll

 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_c0:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_c0:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_c0:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shrxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shlxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = shl i32 -1, %numlowbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_c1_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_c1_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_c1_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_c1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shrxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shlxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %sh_prom = zext i8 %numlowbits to i32
   %mask = shl i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_c2_load(i32* %w, i32 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_c2_load:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_c2_load:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shlxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-TRANSFORM-NEXT:    shrxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shlxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_c2_load:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_c2_load:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shrxl %esi, (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    shlxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %mask = shl i32 -1, %numlowbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_c3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_c3_load_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_c3_load_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shlxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-TRANSFORM-NEXT:    shrxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shlxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_c3_load_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_c3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shrxl %esi, (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    shlxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %sh_prom = zext i8 %numlowbits to i32
   %mask = shl i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_c4_commutative(i32 %val, i32 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_c4_commutative:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_c4_commutative:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_c4_commutative:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_c4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movl $-1, %eax
+; X64-TRANSFORM-NEXT:    shrxl %esi, %edi, %eax
 ; X64-TRANSFORM-NEXT:    shlxl %esi, %eax, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = shl i32 -1, %numlowbits
   %masked = and i32 %val, %mask ; swapped order
   ret i32 %masked
 }
 
 ; 64-bit
 

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_c0:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shrxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shlxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = shl i64 -1, %numlowbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_lowbits64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits64_c1_indexzext:

 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_c1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shrxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shlxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %sh_prom = zext i8 %numlowbits to i64
   %mask = shl i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_lowbits64_c2_load(i64* %w, i64 %numlowbits) nounwind {

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_c2_load:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shrxq %rsi, (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    shlxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %mask = shl i64 -1, %numlowbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_lowbits64_c3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {

 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_c3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shrxq %rsi, (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    shlxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %sh_prom = zext i8 %numlowbits to i64
   %mask = shl i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 

 ; X64-NOTRANSFORM-NEXT:    movq $-1, %rax
 ; X64-NOTRANSFORM-NEXT:    movl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_c4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
-; X64-TRANSFORM-NEXT:    movq $-1, %rax
+; X64-TRANSFORM-NEXT:    shrxq %rsi, %rdi, %rax
 ; X64-TRANSFORM-NEXT:    shlxq %rsi, %rax, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %mask = shl i64 -1, %numlowbits
   %masked = and i64 %val, %mask ; swapped order
   ret i64 %masked
 }
 
 ; ---------------------------------------------------------------------------- ;
 ; Pattern ic. 32-bit

 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_ic0:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movl $32, %eax
 ; X86-TRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_ic0:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $32, %ecx
 ; X64-NOTRANSFORM-NEXT:    subl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_ic0:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $32, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movl $-1, %ecx
+; X64-TRANSFORM-NEXT:    shrxl %eax, %edi, %ecx
 ; X64-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i32 32, %numlowbits
   %mask = shl i32 -1, %numhighbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_ic1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_ic1_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movb $32, %cl
 ; X86-NOTRANSFORM-NEXT:    subb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_ic1_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movb $32, %al
 ; X86-TRANSFORM-NEXT:    subb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_ic1_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movb $32, %cl
 ; X64-NOTRANSFORM-NEXT:    subb %sil, %cl
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_ic1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movb $32, %al
 ; X64-TRANSFORM-NEXT:    subb %sil, %al
-; X64-TRANSFORM-NEXT:    movl $-1, %ecx
+; X64-TRANSFORM-NEXT:    shrxl %eax, %edi, %ecx
 ; X64-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
   %mask = shl i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_ic2_load(i32* %w, i32 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_ic2_load:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movl $32, %ecx
 ; X86-NOTRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %ecx
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_ic2_load:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movl $32, %eax
-; X86-TRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shlxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movl $32, %ecx
+; X86-TRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X86-TRANSFORM-NEXT:    shrxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shlxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_ic2_load:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $32, %ecx
 ; X64-NOTRANSFORM-NEXT:    subl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_ic2_load:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $32, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movl $-1, %ecx
+; X64-TRANSFORM-NEXT:    shrxl %eax, (%rdi), %ecx
 ; X64-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %numhighbits = sub i32 32, %numlowbits
   %mask = shl i32 -1, %numhighbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_ic3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_ic3_load_indexzext:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOTRANSFORM-NEXT:    movb $32, %cl
 ; X86-NOTRANSFORM-NEXT:    subb {{[0-9]+}}(%esp), %cl
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl (%edx), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_ic3_load_indexzext:
 ; X86-TRANSFORM:       # %bb.0:
-; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-TRANSFORM-NEXT:    movb $32, %al
-; X86-TRANSFORM-NEXT:    subb {{[0-9]+}}(%esp), %al
-; X86-TRANSFORM-NEXT:    movl $-1, %edx
-; X86-TRANSFORM-NEXT:    shlxl %eax, %edx, %eax
-; X86-TRANSFORM-NEXT:    andl (%ecx), %eax
+; X86-TRANSFORM-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-TRANSFORM-NEXT:    movb $32, %cl
+; X86-TRANSFORM-NEXT:    subb {{[0-9]+}}(%esp), %cl
+; X86-TRANSFORM-NEXT:    shrxl %ecx, (%eax), %eax
+; X86-TRANSFORM-NEXT:    shlxl %ecx, %eax, %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_ic3_load_indexzext:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movb $32, %cl
 ; X64-NOTRANSFORM-NEXT:    subb %sil, %cl
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_ic3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movb $32, %al
 ; X64-TRANSFORM-NEXT:    subb %sil, %al
-; X64-TRANSFORM-NEXT:    movl $-1, %ecx
+; X64-TRANSFORM-NEXT:    shrxl %eax, (%rdi), %ecx
 ; X64-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X64-TRANSFORM-NEXT:    andl (%rdi), %eax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i32, i32* %w
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
   %mask = shl i32 -1, %sh_prom
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @clear_lowbits32_ic4_commutative(i32 %val, i32 %numlowbits) nounwind {
 ; X86-NOTRANSFORM-LABEL: clear_lowbits32_ic4_commutative:
 ; X86-NOTRANSFORM:       # %bb.0:
 ; X86-NOTRANSFORM-NEXT:    movl $32, %ecx
 ; X86-NOTRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %ecx
 ; X86-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X86-NOTRANSFORM-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X86-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X86-NOTRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NOTRANSFORM-NEXT:    retl
 ;
 ; X86-TRANSFORM-LABEL: clear_lowbits32_ic4_commutative:
 ; X86-TRANSFORM:       # %bb.0:
 ; X86-TRANSFORM-NEXT:    movl $32, %eax
 ; X86-TRANSFORM-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X86-TRANSFORM-NEXT:    movl $-1, %ecx
+; X86-TRANSFORM-NEXT:    shrxl %eax, {{[0-9]+}}(%esp), %ecx
 ; X86-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X86-TRANSFORM-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-TRANSFORM-NEXT:    retl
 ;
 ; X64-NOTRANSFORM-LABEL: clear_lowbits32_ic4_commutative:
 ; X64-NOTRANSFORM:       # %bb.0:
 ; X64-NOTRANSFORM-NEXT:    movl $32, %ecx
 ; X64-NOTRANSFORM-NEXT:    subl %esi, %ecx
 ; X64-NOTRANSFORM-NEXT:    movl $-1, %eax
 ; X64-NOTRANSFORM-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NOTRANSFORM-NEXT:    shll %cl, %eax
 ; X64-NOTRANSFORM-NEXT:    andl %edi, %eax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits32_ic4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $32, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movl $-1, %ecx
+; X64-TRANSFORM-NEXT:    shrxl %eax, %edi, %ecx
 ; X64-TRANSFORM-NEXT:    shlxl %eax, %ecx, %eax
-; X64-TRANSFORM-NEXT:    andl %edi, %eax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i32 32, %numlowbits
   %mask = shl i32 -1, %numhighbits
   %masked = and i32 %val, %mask ; swapped order
   ret i32 %masked
 }
 
 ; 64-bit

 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_ic0:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $64, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movq $-1, %rcx
+; X64-TRANSFORM-NEXT:    shrxq %rax, %rdi, %rcx
 ; X64-TRANSFORM-NEXT:    shlxq %rax, %rcx, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i64 64, %numlowbits
   %mask = shl i64 -1, %numhighbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @clear_lowbits64_ic1_indexzext(i64 %val, i8 %numlowbits) nounwind {

 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_ic1_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movb $64, %al
 ; X64-TRANSFORM-NEXT:    subb %sil, %al
-; X64-TRANSFORM-NEXT:    movq $-1, %rcx
+; X64-TRANSFORM-NEXT:    shrxq %rax, %rdi, %rcx
 ; X64-TRANSFORM-NEXT:    shlxq %rax, %rcx, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
   %mask = shl i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 

 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_ic2_load:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $64, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movq $-1, %rcx
+; X64-TRANSFORM-NEXT:    shrxq %rax, (%rdi), %rcx
 ; X64-TRANSFORM-NEXT:    shlxq %rax, %rcx, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %numhighbits = sub i64 64, %numlowbits
   %mask = shl i64 -1, %numhighbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 

 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_ic3_load_indexzext:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movb $64, %al
 ; X64-TRANSFORM-NEXT:    subb %sil, %al
-; X64-TRANSFORM-NEXT:    movq $-1, %rcx
+; X64-TRANSFORM-NEXT:    shrxq %rax, (%rdi), %rcx
 ; X64-TRANSFORM-NEXT:    shlxq %rax, %rcx, %rax
-; X64-TRANSFORM-NEXT:    andq (%rdi), %rax
 ; X64-TRANSFORM-NEXT:    retq
   %val = load i64, i64* %w
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
   %mask = shl i64 -1, %sh_prom
   %masked = and i64 %mask, %val
   ret i64 %masked
 }

 ; X64-NOTRANSFORM-NEXT:    shlq %cl, %rax
 ; X64-NOTRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-NOTRANSFORM-NEXT:    retq
 ;
 ; X64-TRANSFORM-LABEL: clear_lowbits64_ic4_commutative:
 ; X64-TRANSFORM:       # %bb.0:
 ; X64-TRANSFORM-NEXT:    movl $64, %eax
 ; X64-TRANSFORM-NEXT:    subl %esi, %eax
-; X64-TRANSFORM-NEXT:    movq $-1, %rcx
+; X64-TRANSFORM-NEXT:    shrxq %rax, %rdi, %rcx
 ; X64-TRANSFORM-NEXT:    shlxq %rax, %rcx, %rax
-; X64-TRANSFORM-NEXT:    andq %rdi, %rax
 ; X64-TRANSFORM-NEXT:    retq
   %numhighbits = sub i64 64, %numlowbits
   %mask = shl i64 -1, %numhighbits
   %masked = and i64 %val, %mask ; swapped order
   ret i64 %masked
 }
 
 ; ---------------------------------------------------------------------------- ;