[llvm-exegesis] Add uop computation for more X87 instruction classes.

[courbet]

Summary

This allows measuring comparisons (UCOM_FpIr32,UCOM_Fpr32,...),
conditional moves (CMOVBE_Fp32,...)

[gchatelet]

tools/llvm-exegesis/lib/BenchmarkRunner.cpp

224

llvm::formatv("{0}, repeating an unconstrained assignment", Msg);

tools/llvm-exegesis/lib/X86/Target.cpp

141

Explain the magic value.

148

?

171

Reg and RegSizeBytes could theoretically be out of sync. Should RegSizeBytes be computed from Reg?

182

Maybe create a constant for 4 to give it semantic.

199

fillStackSpace? fillScratchMemory feels too broad and disconnected from allocateStackSpace

[courbet]

rebase

[courbet]

Address review comments.

[courbet]

Thanks, PTAL.

tools/llvm-exegesis/lib/X86/Target.cpp

171

We could take that RegClass and do RegClass.MC.RegsSize, but is feels awkward.

[courbet]

clang-format

[courbet]

Thanks !

tools/llvm-exegesis/lib/BenchmarkRunner.h

struct BenchmarkConfiguration {
 
   // Informations about how this configuration was built.
   std::string Info;
 };
 
 // Common code for all benchmark modes.
 class BenchmarkRunner {
 public:
-  explicit BenchmarkRunner(const LLVMState &State, InstructionBenchmark::ModeE Mode);
+  explicit BenchmarkRunner(const LLVMState &State,
+                           InstructionBenchmark::ModeE Mode);
 
   virtual ~BenchmarkRunner();
 
   llvm::Expected<std::vector<InstructionBenchmark>>
   run(unsigned Opcode, unsigned NumRepetitions);
 
   // Given a snippet, computes which registers the setup code needs to define.
   std::vector<unsigned>
   computeRegsToDef(const std::vector<InstructionInstance> &Snippet) const;
 
 protected:
   const LLVMState &State;
   const RegisterAliasingTrackerCache RATC;
 
-  llvm::Expected<SnippetPrototype> generateSelfAliasingPrototype(
-      const Instruction &Instr) const;
+  // Generates a single instruction prototype that has a self-dependency.
+  llvm::Expected<SnippetPrototype>
+  generateSelfAliasingPrototype(const Instruction &Instr) const;
+  // Generates a single instruction prototype without assignment constraints.
+  llvm::Expected<SnippetPrototype>
+  generateUnconstrainedPrototype(const Instruction &Instr,
+                                 llvm::StringRef Msg) const;
 
 private:
   // API to be implemented by subclasses.
   virtual llvm::Expected<SnippetPrototype>
-    generatePrototype(unsigned Opcode) const = 0;
 
   virtual std::vector<BenchmarkMeasure>
-    runMeasurements(const ExecutableFunction &EF,
-                    const unsigned NumRepetitions) const = 0;
 
   // Internal helpers.
   InstructionBenchmark runOne(const BenchmarkConfiguration &Configuration,
                               unsigned Opcode, unsigned NumRepetitions) const;
 
   // Calls generatePrototype and expands the SnippetPrototype into one or more
   // BenchmarkConfiguration.
   llvm::Expected<std::vector<BenchmarkConfiguration>>
   generateConfigurations(unsigned Opcode) const;
 
-
   llvm::Expected<std::string>
   writeObjectFile(const BenchmarkConfiguration::Setup &Setup,
                   llvm::ArrayRef<llvm::MCInst> Code) const;
 
   const InstructionBenchmark::ModeE Mode;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_BENCHMARKRUNNER_H

tools/llvm-exegesis/lib/BenchmarkRunner.cpp

if (llvm::Error E = llvm::errorCodeToError(llvm::sys::fs::createTemporaryFile(
           "snippet", "o", ResultFD, ResultPath)))
     return std::move(E);
   llvm::raw_fd_ostream OFS(ResultFD, true /*ShouldClose*/);
   assembleToStream(State.getExegesisTarget(), State.createTargetMachine(),
                    Setup.RegsToDef, Code, OFS);
   return ResultPath.str();
 }
 
-llvm::Expected<SnippetPrototype> BenchmarkRunner::generateSelfAliasingPrototype(
-    const Instruction &Instr) const {
+llvm::Expected<SnippetPrototype>
+BenchmarkRunner::generateSelfAliasingPrototype(const Instruction &Instr) const {
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
     return llvm::make_error<BenchmarkFailure>("empty self aliasing");
   }
   SnippetPrototype Prototype;
   InstructionInstance II(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
     Prototype.Explanation = "implicit Self cycles, picking random values.";
   } else {
     Prototype.Explanation =
         "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice II in the following call.
     setRandomAliasing(SelfAliasing, II, II);
   }
   Prototype.Snippet.push_back(std::move(II));
   return std::move(Prototype);
 }
 
+llvm::Expected<SnippetPrototype>
+BenchmarkRunner::generateUnconstrainedPrototype(const Instruction &Instr,
+                                                llvm::StringRef Msg) const {
+  SnippetPrototype Prototype;
+  Prototype.Explanation = Msg.str();
+  Prototype.Explanation += ", repeating an unconstrained assignment";
+  Prototype.Snippet.emplace_back(Instr);
+  return std::move(Prototype);
+}
 } // namespace exegesis

tools/llvm-exegesis/lib/Uops.cpp

 llvm::Expected<SnippetPrototype>
 UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   const auto &InstrDesc = State.getInstrInfo().get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
-    SnippetPrototype Prototype;
-    Prototype.Explanation = "instruction is parallel, repeating a random one.";
-    Prototype.Snippet.emplace_back(Instr);
-    return std::move(Prototype);
+    return generateUnconstrainedPrototype(Instr, "instruction is parallel");
   }
   if (SelfAliasing.hasImplicitAliasing()) {
-    SnippetPrototype Prototype;
-    Prototype.Explanation = "instruction is serial, repeating a random one.";
-    Prototype.Snippet.emplace_back(Instr);
-    return std::move(Prototype);
+    return generateUnconstrainedPrototype(Instr, "instruction is serial");
   }
   const auto TiedVariables = getTiedVariables(Instr);
   if (!TiedVariables.empty()) {
     if (TiedVariables.size() > 1)
       return llvm::make_error<llvm::StringError>(
           "Infeasible : don't know how to handle several tied variables",
           llvm::inconvertibleErrorCode());
     const Variable *Var = TiedVariables.front();

tools/llvm-exegesis/lib/X86/Target.cpp

generatePrototype(unsigned Opcode) const override {
     // Handle X87.
     const auto &InstrDesc = InstrInfo.get(Opcode);
     const unsigned FPInstClass = InstrDesc.TSFlags & llvm::X86II::FPTypeMask;
     const Instruction Instr(InstrDesc, this->RATC);
     switch (FPInstClass) {
     case llvm::X86II::NotFP:
       break;
     case llvm::X86II::ZeroArgFP:
-      return Impl::handleZeroArgFP(Instr);
+      return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
     case llvm::X86II::OneArgFP:
-      return Impl::handleOneArgFP(Instr); // fstp ST(0)
+      return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
     case llvm::X86II::OneArgFPRW:
     case llvm::X86II::TwoArgFP: {
       // These are instructions like
       //   - `ST(0) = fsqrt(ST(0))` (OneArgFPRW)
       //   - `ST(0) = ST(0) + ST(i)` (TwoArgFP)
       // They are intrinsically serial and do not modify the state of the stack.
       // We generate the same code for latency and uops.
       return this->generateSelfAliasingPrototype(Instr);
     }
     case llvm::X86II::CompareFP:
       return Impl::handleCompareFP(Instr);
     case llvm::X86II::CondMovFP:
       return Impl::handleCondMovFP(Instr);
     case llvm::X86II::SpecialFP:
-      return Impl::handleSpecialFP(Instr);
+      return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
     default:
       llvm_unreachable("Unknown FP Type!");
     }
 
     // Fallback to generic implementation.
     return Impl::Base::generatePrototype(Opcode);
   }
 };
 
 class X86LatencyImpl : public LatencyBenchmarkRunner {
 protected:
   using Base = LatencyBenchmarkRunner;
   using Base::Base;
   llvm::Expected<SnippetPrototype>
-  handleZeroArgFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
-  }
-  llvm::Expected<SnippetPrototype>
-  handleOneArgFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
-  }
-  llvm::Expected<SnippetPrototype>
   handleCompareFP(const Instruction &Instr) const {
     return llvm::make_error<BenchmarkFailure>("Unsupported x87 CompareFP");
   }
   llvm::Expected<SnippetPrototype>
   handleCondMovFP(const Instruction &Instr) const {
     return llvm::make_error<BenchmarkFailure>("Unsupported x87 CondMovFP");
   }
-  llvm::Expected<SnippetPrototype>
-  handleSpecialFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
-  }
 };
 
 class X86UopsImpl : public UopsBenchmarkRunner {
 protected:
   using Base = UopsBenchmarkRunner;
   using Base::Base;
-  llvm::Expected<SnippetPrototype>
-  handleZeroArgFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
-  }
-  llvm::Expected<SnippetPrototype>
-  handleOneArgFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
-  }
+  // We can compute uops for any FP instruction that does not grow or shrink the
+  // stack (either do not touch the stack or push as much as they pop).
   llvm::Expected<SnippetPrototype>
   handleCompareFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CompareFP");
+    return generateUnconstrainedPrototype(
+        Instr, "instruction does not grow/shrink the FP stack");
   }
   llvm::Expected<SnippetPrototype>
   handleCondMovFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CondMovFP");
-  }
-  llvm::Expected<SnippetPrototype>
-  handleSpecialFP(const Instruction &Instr) const {
-    return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
+    return generateUnconstrainedPrototype(
+        Instr, "instruction does not grow/shrink the FP stack");
   }
 };
 
 class ExegesisX86Target : public ExegesisTarget {
   void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override {
     // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F.
     // FIXME: Enable when the exegesis assembler no longer does
     // Properties.reset(TracksLiveness);
     PM.add(llvm::createX86FloatingPointStackifierPass());
   }
 
-  std::vector<llvm::MCInst>
-  setRegToConstant(unsigned Reg) const override {
+  std::vector<llvm::MCInst> setRegToConstant(unsigned Reg) const override {
     if (llvm::X86::GR8RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::GR16RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::GR32RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)};
std::vector<llvm::MCInst> setRegToConstant(unsigned Reg) const override {
     if (llvm::X86::VR512RegClass.contains(Reg)) {
       return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm);
     }
     if (llvm::X86::RFP32RegClass.contains(Reg) ||
         llvm::X86::RFP64RegClass.contains(Reg) ||
         llvm::X86::RFP80RegClass.contains(Reg)) {
       return setVectorRegToConstant(Reg, 8, llvm::X86::LD_Fp64m);
     }
+    if (Reg == llvm::X86::EFLAGS) {
+      constexpr const uint32_t kImmValue = 0x00007002u;
+      std::vector<llvm::MCInst> Result;
+      Result.push_back(allocateStackSpace(8));
+      Result.push_back(fillScratchMemory(llvm::X86::MOV64mi32, 0, kImmValue));
+      Result.push_back(llvm::MCInstBuilder(llvm::X86::POPF64)); // Also pops.
+      return Result;
+    }
+    llvm::errs() << Reg << "\n";
     return {};
   }
 
   std::unique_ptr<BenchmarkRunner>
   createLatencyBenchmarkRunner(const LLVMState &State) const override {
-    return llvm::make_unique<X86BenchmarkRunner<X86LatencyImpl>>(
-        State);
+    return llvm::make_unique<X86BenchmarkRunner<X86LatencyImpl>>(State);
   }
 
   std::unique_ptr<BenchmarkRunner>
   createUopsBenchmarkRunner(const LLVMState &State) const override {
     return llvm::make_unique<X86BenchmarkRunner<X86UopsImpl>>(State);
   }
 
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
   }
 
 private:
   // setRegToConstant() specialized for a vector register of size
   // `RegSizeBytes`. `RMOpcode` is the opcode used to do a memory -> vector
   // register load.
   static std::vector<llvm::MCInst>
   setVectorRegToConstant(const unsigned Reg, const unsigned RegSizeBytes,
                          const unsigned RMOpcode) {
     // There is no instruction to directly set XMM, go through memory.
     // Since vector values can be interpreted as integers of various sizes (8
     // to 64 bits) as well as floats and double, so we chose an immediate
     // value that has set bits for all byte values and is a normal float/
     // double. 0x40404040 is ~32.5 when interpreted as a double and ~3.0f when
     // interpreted as a float.
-    constexpr const uint64_t kImmValue = 0x40404040ull;
+    constexpr const uint32_t kImmValue = 0x40404040u;
     std::vector<llvm::MCInst> Result;
-    // Allocate scratch memory on the stack.
-    Result.push_back(llvm::MCInstBuilder(llvm::X86::SUB64ri8)
-                         .addReg(llvm::X86::RSP)
-                         .addReg(llvm::X86::RSP)
-                         .addImm(RegSizeBytes));
-    // Fill scratch memory.
-    for (unsigned Disp = 0; Disp < RegSizeBytes; Disp += 4) {
-      Result.push_back(llvm::MCInstBuilder(llvm::X86::MOV32mi)
-                           // Address = ESP
-                           .addReg(llvm::X86::RSP) // BaseReg
-                           .addImm(1)              // ScaleAmt
-                           .addReg(0)              // IndexReg
-                           .addImm(Disp)           // Disp
-                           .addReg(0)              // Segment
-                           // Immediate.
-                           .addImm(kImmValue));
-    }
-    // Load Reg from scratch memory.
-    Result.push_back(llvm::MCInstBuilder(RMOpcode)
-                         .addReg(Reg)
-                         // Address = ESP
-                         .addReg(llvm::X86::RSP) // BaseReg
-                         .addImm(1)              // ScaleAmt
-                         .addReg(0)              // IndexReg
-                         .addImm(0)              // Disp
-                         .addReg(0));            // Segment
-    // Release scratch memory.
-    Result.push_back(llvm::MCInstBuilder(llvm::X86::ADD64ri8)
-                         .addReg(llvm::X86::RSP)
-                         .addReg(llvm::X86::RSP)
-                         .addImm(RegSizeBytes));
-    return Result;
+    Result.push_back(allocateStackSpace(RegSizeBytes));
+    for (unsigned Disp = 0; Disp < RegSizeBytes; Disp += 4) {
+      Result.push_back(fillScratchMemory(llvm::X86::MOV32mi, Disp, kImmValue));
+    }
+    Result.push_back(loadToReg(Reg, RMOpcode));
+    Result.push_back(releaseStackSpace(RegSizeBytes));
+    return Result;
+  }
+
+  // Allocates scratch memory on the stack.
+  static llvm::MCInst allocateStackSpace(unsigned Bytes) {
+    return llvm::MCInstBuilder(llvm::X86::SUB64ri8)
+        .addImm(Bytes);
+  }
+
+  // Fills scratch memory at offset `OffsetBytes` with value `Imm`.
+  static llvm::MCInst fillScratchMemory(unsigned MovOpcode,
+                                        unsigned OffsetBytes, uint64_t Imm) {
+    return llvm::MCInstBuilder(MovOpcode)
+        .addImm(OffsetBytes)    // Disp
+        .addImm(Imm);
+
+  // Loads scratch memory into register `Reg` using opcode `RMOpcode`.
+  static llvm::MCInst loadToReg(unsigned Reg, unsigned RMOpcode) {
+    return llvm::MCInstBuilder(RMOpcode)
+        .addReg(0);             // Segment
+  }
+
+  // Releases scratch memory.
+  static llvm::MCInst releaseStackSpace(unsigned Bytes) {
+    return llvm::MCInstBuilder(llvm::X86::ADD64ri8)
+        .addImm(Bytes);
   }
 };
 
 } // namespace
 
 static ExegesisTarget *getTheExegesisX86Target() {
   static ExegesisX86Target Target;
   return &Target;
 }
 
 void InitializeX86ExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisX86Target());
 }
 
 } // namespace exegesis

unittests/tools/llvm-exegesis/X86/TargetTest.cpp

TEST_F(X86TargetTest, SetRegToConstantGPR) {
   const auto Insts = Target_->setRegToConstant(llvm::X86::EAX);
   EXPECT_THAT(Insts, SizeIs(1));
   EXPECT_EQ(Insts[0].getOpcode(), llvm::X86::MOV32ri);
   EXPECT_EQ(Insts[0].getOperand(0).getReg(), llvm::X86::EAX);
 }
 
 TEST_F(X86TargetTest, SetRegToConstantXMM) {
   const auto Insts = Target_->setRegToConstant(llvm::X86::XMM1);
-  EXPECT_THAT(Insts, SizeIs(Gt(0U)));
+  EXPECT_THAT(Insts, SizeIs(Gt(4U)));
 }
 
 } // namespace
 } // namespace exegesis