[ARM] [Assembler] Support negative immediates: cover few missing cases

[voltur01]

Summary

Support for negative immediates was implemented in
https://reviews.llvm.org/rL298380, however few instruction options were missing.

This change adds negative immediates support and respective tests
for the following:

ADD
ADDS
ADDS.W
AND.W
ANDS
BIC.W
BICS
BICS.W
SUB
SUBS
SUBS.W

[olista01]

LGTM

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
                  (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"addw${p} $rd, $rn, $imm",
                  (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
                  (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"subw${p} $rd, $rn, $imm",
                  (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
+def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
+                 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
+                 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"sub${p} $rd, $rn, $imm",
+                 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
 // RSB
 defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb", sub>;
 
 // FIXME: Eliminate them if we can write def : Pat patterns which defines
 // CPSR and the implicit def of CPSR is not needed.
 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
                   (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
 // Same for AND <--> BIC
 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
                   (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"bic${s}${p} $Rdn, $imm",
                   (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
+def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
+                  (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
+                           pred:$p, cc_out:$s)>;
+def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",
+                  (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
+                           pred:$p, cc_out:$s)>;
 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
                   (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"and${s}${p} $Rdn, $imm",
                   (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
+def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
+                  (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
+                           pred:$p, cc_out:$s)>;
+def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",
+                  (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
+                           pred:$p, cc_out:$s)>;
 // And ORR <--> ORN
 def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",
                   (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"orn${s}${p} $Rdn, $imm",
                   (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool isImm0_508s4Neg() const {
     // explicitly exclude zero. we want that to use the normal 0_508 version.
     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
   }
 
   bool isImm0_4095Neg() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
-    int64_t Value = -CE->getValue();
+    // isImm0_4095Neg is used with 32-bit immediates only.
+    // 32-bit immediates are zero extended to 64-bit when parsed,
+    // thus simple -CE->getValue() results in a big negative number,
+    // not a small positive number as intended
+    if ((CE->getValue() >> 32) > 0) return false;
+    uint32_t Value = -static_cast<uint32_t>(CE->getValue());
     return Value > 0 && Value < 4096;
   }
 
   bool isImm0_7() const {
     return isImmediate<0, 7>();
   }
 
   bool isImm1_16() const {
void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
   }
 
   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The operand is actually an imm0_4095, but we have its
     // negation in the assembly source, so twiddle it here.
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
-    Inst.addOperand(MCOperand::createImm(-CE->getValue()));
+    Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
   }
 
   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
       return;
     }
 

llvm/trunk/test/MC/ARM/negative-immediates.s

 # CHECK-DISABLED: SBC
   SUB r0, r1, #0xFFFFFF01
 # CHECK: add r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUB
 
 .thumb
 
+  ADD r0, r1, #0xFFFFFF00
+# CHECK: subw r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: ADD
+  ADDS r0, r1, #0xFFFFFF00
+# CHECK: subs.w r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: ADDS
+  ADDS.W r0, r1, #0xFFFFFF00
+# CHECK: subs.w r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: ADDS.W
   ADC r0, r1, #0xFFFFFF00
 # CHECK: sbc r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ADC
   ADC r0, r1, #0xFFFF00FF
 # CHECK: sbc r0, r1, #65280
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ADC
# CHECK-DISABLED: ADD.W
   AND r0, r1, #0xFFFFFF00
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: AND
 # CHECK: bic r0, r1, #255
   AND r0, r1, #0xFEFFFEFF
 # CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20]
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: AND
+  AND.W r0, r1, #0xFFFFFF00
+# CHECK: bic r0, r1, #255
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: AND.W
+  ANDS r0, r1, #0xFFFFFF00
+# CHECK: bics r0, r1, #255
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: ANDS
   BIC r0, r1, #0xFFFFFF00
 # CHECK: and r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: BIC
+  BIC.W r0, r1, #0xFFFFFF00
+# CHECK: and r0, r1, #255
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: BIC.W
+  BICS r0, r1, #0xFFFFFF00
+# CHECK: ands r0, r1, #255
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: BICS
+  BICS.W r0, r1, #0xFFFFFF00
+# CHECK: ands r0, r1, #255
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: BICS.W
   BIC r0, r1, #0xFEFFFEFF
 # CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20]
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: BIC
   ORR r0, r1, #0xFFFFFF00
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ORR
 # CHECK: orn r0, r1, #255
# CHECK-DISABLED: SBC
   SUBW r0, r1, #0xFFFFFF01
 # CHECK: addw r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUBW
   SUB.W r0, r1, #0xFFFFFF01
 # CHECK: add.w r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUB.W
+  SUB r0, r1, #0xFFFFFF00
+# CHECK: addw r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: SUB
+  SUBS r0, r1, #0xFFFFFF00
+# CHECK: adds.w r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: SUBS
+  SUBS.W r0, r1, #0xFFFFFF00
+# CHECK: adds.w r0, r1, #256
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: SUBS.W
+
+  ADD r0, r1, #-13
+# CHECK: subw r0, r1, #13
+# CHECK-DISABLED: note: instruction requires: NegativeImmediates
+# CHECK-DISABLED: ADD