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[Sparc] Add support for the cycle counter available in GR740
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Authored by dcederman on Jun 27 2018, 5:31 AM.

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Summary

The GR740 provides an up cycle counter in the registers ASR22 and ASR23. As these registers can not be read together atomically we only use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register holds the 32 LSBs of the up-counter.

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rL LLVM

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dcederman created this revision.Jun 27 2018, 5:31 AM
jyknight accepted this revision.Jul 13 2018, 11:59 AM

I suppose if it was useful, you could use a loop to read both halves of the counter safely, e.g. upper=ASR22; loop: lower=ASR23; newupper=ASR22; if (newupper != upper) { upper = newupper; goto loop; }}.

But I have no idea if that would be useful, so this seems fine.

This revision is now accepted and ready to land.Jul 13 2018, 11:59 AM
This revision was automatically updated to reflect the committed changes.
dcederman updated this revision to Diff 160357.Aug 13 2018, 7:56 AM

Reserved register ASR23 to avoid error stating that register ASR23 is "an undefined physical register". Not sure if this is the correct solution, so putting this up for review again.

dcederman reopened this revision.Aug 13 2018, 7:56 AM
This revision is now accepted and ready to land.Aug 13 2018, 7:56 AM

I wonder if we perhaps shouldn't've modeled the ASR registers as registers at all (other than Y -- it's "special"). That seems to be what other targets do with their MSRs. Not sure if it really matters...

Anyways, having it be marked reserved seems correct. It may be simpler to just always mark ASR1-31 as reserved, though?

dcederman updated this revision to Diff 161429.Aug 20 2018, 1:04 AM

Reserving registers ASR1-ASR31

LGTM.

It's possibly only theoretical at the moment, since I don't know if anything both supports this and is little endian, but --
On a little endian system, will the registers be swapped; that is, would ASR22 hold the 32 LSB instead of ASR23?

LGTM.

It's possibly only theoretical at the moment, since I don't know if anything both supports this and is little endian, but --
On a little endian system, will the registers be swapped; that is, would ASR22 hold the 32 LSB instead of ASR23?

We are not aware of any little endian system that supports this at the moment, but as the registers cannot be read together as a 64-bit value we do not think there is a reason to swap the registers for little endian systems.

This revision was automatically updated to reflect the committed changes.