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Differential D48630

AMDGPU: Fix assert on aggregate type kernel arguments
ClosedPublic

Authored by arsenm on Jun 27 2018, 4:54 AM.

Details

Reviewers
rampitec
Summary

Just fix the crash for now by not doing the optimization since
figuring out how to properly convert the bits for an arbitrary
struct is a pain.

Diff Detail

Event Timeline

arsenm created this revision.Jun 27 2018, 4:54 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptJun 27 2018, 4:54 AM
arsenm updated this revision to Diff 153046.Jun 27 2018, 5:01 AM

Fix special case of having a single unsized kernel argument

rampitec accepted this revision.Jun 27 2018, 11:27 AM

LGTM

This revision is now accepted and ready to land.Jun 27 2018, 11:27 AM
arsenm closed this revision.Jun 28 2018, 3:25 AM

r335827

Revision Contents

PathSize
lib/
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
171 lines

Diff 153046

lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Linesbool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
// Minimum alignment for kern segment is 16. // Minimum alignment for kern segment is 16.
unsigned KernArgBaseAlign = std::max(16u, DL.getABITypeAlignment(ArgStructTy)); unsigned KernArgBaseAlign = std::max(16u, DL.getABITypeAlignment(ArgStructTy));
const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(F); const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(F);
// FIXME: Alignment is broken broken with explicit arg offset.; // FIXME: Alignment is broken broken with explicit arg offset.;
const uint64_t TotalKernArgSize = BaseOffset + const uint64_t TotalKernArgSize = BaseOffset +
ST.getKernArgSegmentSize(F, DL.getTypeAllocSize(ArgStructTy)); ST.getKernArgSegmentSize(F, DL.getTypeAllocSize(ArgStructTy));
if (TotalKernArgSize == 0)
return false;
CallInst *KernArgSegment = CallInst *KernArgSegment =
Builder.CreateIntrinsic(Intrinsic::amdgcn_kernarg_segment_ptr, nullptr, Builder.CreateIntrinsic(Intrinsic::amdgcn_kernarg_segment_ptr, nullptr,
F.getName() + ".kernarg.segment"); F.getName() + ".kernarg.segment");
KernArgSegment->addAttribute(AttributeList::ReturnIndex, Attribute::NonNull); KernArgSegment->addAttribute(AttributeList::ReturnIndex, Attribute::NonNull);
KernArgSegment->addAttribute(AttributeList::ReturnIndex, KernArgSegment->addAttribute(AttributeList::ReturnIndex,
Attribute::getWithDereferenceableBytes(Ctx, TotalKernArgSize)); Attribute::getWithDereferenceableBytes(Ctx, TotalKernArgSize));
Show All 37 Lines for (Argument &Arg : F.args()) {
bool IsExtArg = Size < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) && bool IsExtArg = Size < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) &&
!ST.isAmdHsaOS(); !ST.isAmdHsaOS();
int64_t EltOffset = Layout->getElementOffset(Arg.getArgNo()); int64_t EltOffset = Layout->getElementOffset(Arg.getArgNo());
int64_t AlignDownOffset = alignDown(EltOffset, 4); int64_t AlignDownOffset = alignDown(EltOffset, 4);
int64_t OffsetDiff = EltOffset - AlignDownOffset; int64_t OffsetDiff = EltOffset - AlignDownOffset;
unsigned AdjustedAlign = MinAlign(KernArgBaseAlign, AlignDownOffset); unsigned AdjustedAlign = MinAlign(KernArgBaseAlign, AlignDownOffset);
Value *ArgPtr; Value *ArgPtr;
if (Size < 32) { if (Size < 32 && !ArgTy->isAggregateType()) { // FIXME: Handle aggregate types
// Since we don't have sub-dword scalar loads, avoid doing an extload by // Since we don't have sub-dword scalar loads, avoid doing an extload by
// loading earlier than the argument address, and extracting the relevant // loading earlier than the argument address, and extracting the relevant
// bits. // bits.
// //
// Additionally widen any sub-dword load to i32 even if suitably aligned, // Additionally widen any sub-dword load to i32 even if suitably aligned,
// so that CSE between different argument loads works easily. // so that CSE between different argument loads works easily.
ArgPtr = Builder.CreateConstGEP1_64(KernArgBase, AlignDownOffset); ArgPtr = Builder.CreateConstGEP1_64(KernArgBase, AlignDownOffset);
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines if (isa<PointerType>(ArgTy)) {
MDNode::get(Ctx, MDNode::get(Ctx,
MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(), MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(),
ParamAlign)))); ParamAlign))));
} }
} }
// TODO: Convert noalias arg to !noalias // TODO: Convert noalias arg to !noalias
if (Size < 32) { if (Size < 32 && !ArgTy->isAggregateType()) {
if (IsExtArg && OffsetDiff == 0) { if (IsExtArg && OffsetDiff == 0) {
Type *I32Ty = Builder.getInt32Ty(); Type *I32Ty = Builder.getInt32Ty();
bool IsSext = Arg.hasSExtAttr(); bool IsSext = Arg.hasSExtAttr();
Metadata *LowAndHigh[] = { Metadata *LowAndHigh[] = {
ConstantAsMetadata::get( ConstantAsMetadata::get(
ConstantInt::get(I32Ty, IsSext ? minIntN(Size) : 0)), ConstantInt::get(I32Ty, IsSext ? minIntN(Size) : 0)),
ConstantAsMetadata::get( ConstantAsMetadata::get(
ConstantInt::get(I32Ty, ConstantInt::get(I32Ty,
Show All 38 Lines

test/CodeGen/AMDGPU/lower-kernargs.ll

Show First 20 Lines • Show All 1,260 Lines • ▼ Show 20 Lines
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.*]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.*]], i8 addrspace(1)* addrspace(1)* undef
; MESA-NEXT: ret void ; MESA-NEXT: ret void
; ;
store volatile i8 addrspace(1)* %ptr0, i8 addrspace(1)* addrspace(1)* undef store volatile i8 addrspace(1)* %ptr0, i8 addrspace(1)* addrspace(1)* undef
store volatile i8 addrspace(1)* %ptr1, i8 addrspace(1)* addrspace(1)* undef store volatile i8 addrspace(1)* %ptr1, i8 addrspace(1)* addrspace(1)* undef
ret void ret void
} }
define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {
; HSA-LABEL: @struct_i8_i8_arg(
; HSA-NEXT: entry:
; HSA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(4)* [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]] to [[STRUCT_I8_I8_ARG:%.*]] addrspace(4)*
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[STRUCT_I8_I8_ARG]], [[STRUCT_I8_I8_ARG]] addrspace(4)* [[TMP0]], i32 0, i32 0
; HSA-NEXT: [[IN_LOAD:%.*]] = load { i8, i8 }, { i8, i8 } addrspace(4)* [[IN_KERNARG_OFFSET]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; HSA-NEXT: ret void
;
; MESA-LABEL: @struct_i8_i8_arg(
; MESA-NEXT: entry:
; MESA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to [[STRUCT_I8_I8_ARG:%.*]] addrspace(4)*
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[STRUCT_I8_I8_ARG]], [[STRUCT_I8_I8_ARG]] addrspace(4)* [[TMP1]], i32 0, i32 0
; MESA-NEXT: [[IN_LOAD:%.*]] = load { i8, i8 }, { i8, i8 } addrspace(4)* [[IN_KERNARG_OFFSET]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; MESA-NEXT: ret void
;
entry:
%elt0 = extractvalue {i8, i8} %in, 0
%elt1 = extractvalue {i8, i8} %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i8 %elt1, i8 addrspace(1)* null, align 4
ret void
}
define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {
; HSA-LABEL: @struct_i8_i16_arg(
; HSA-NEXT: entry:
; HSA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(4)* [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]] to [[STRUCT_I8_I16_ARG:%.*]] addrspace(4)*
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[STRUCT_I8_I16_ARG]], [[STRUCT_I8_I16_ARG]] addrspace(4)* [[TMP0]], i32 0, i32 0
; HSA-NEXT: [[IN_LOAD:%.*]] = load { i8, i16 }, { i8, i16 } addrspace(4)* [[IN_KERNARG_OFFSET]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4
; HSA-NEXT: ret void
;
; MESA-LABEL: @struct_i8_i16_arg(
; MESA-NEXT: entry:
; MESA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to [[STRUCT_I8_I16_ARG:%.*]] addrspace(4)*
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[STRUCT_I8_I16_ARG]], [[STRUCT_I8_I16_ARG]] addrspace(4)* [[TMP1]], i32 0, i32 0
; MESA-NEXT: [[IN_LOAD:%.*]] = load { i8, i16 }, { i8, i16 } addrspace(4)* [[IN_KERNARG_OFFSET]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4
; MESA-NEXT: ret void
;
entry:
%elt0 = extractvalue {i8, i16} %in, 0
%elt1 = extractvalue {i8, i16} %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i16 %elt1, i16 addrspace(1)* null, align 4
ret void
}
define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {
; HSA-LABEL: @array_2xi8_arg(
; HSA-NEXT: entry:
; HSA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(4)* [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]] to [[ARRAY_2XI8_ARG:%.*]] addrspace(4)*
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[ARRAY_2XI8_ARG]], [[ARRAY_2XI8_ARG]] addrspace(4)* [[TMP0]], i32 0, i32 0
; HSA-NEXT: [[IN_LOAD:%.*]] = load [2 x i8], [2 x i8] addrspace(4)* [[IN_KERNARG_OFFSET]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; HSA-NEXT: ret void
;
; MESA-LABEL: @array_2xi8_arg(
; MESA-NEXT: entry:
; MESA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to [[ARRAY_2XI8_ARG:%.*]] addrspace(4)*
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[ARRAY_2XI8_ARG]], [[ARRAY_2XI8_ARG]] addrspace(4)* [[TMP1]], i32 0, i32 0
; MESA-NEXT: [[IN_LOAD:%.*]] = load [2 x i8], [2 x i8] addrspace(4)* [[IN_KERNARG_OFFSET]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; MESA-NEXT: ret void
;
entry:
%elt0 = extractvalue [2 x i8] %in, 0
%elt1 = extractvalue [2 x i8] %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i8 %elt1, i8 addrspace(1)* null, align 4
ret void
}
define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {
; HSA-LABEL: @array_2xi1_arg(
; HSA-NEXT: entry:
; HSA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(4)* [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]] to [[ARRAY_2XI1_ARG:%.*]] addrspace(4)*
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[ARRAY_2XI1_ARG]], [[ARRAY_2XI1_ARG]] addrspace(4)* [[TMP0]], i32 0, i32 0
; HSA-NEXT: [[IN_LOAD:%.*]] = load [2 x i1], [2 x i1] addrspace(4)* [[IN_KERNARG_OFFSET]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
; HSA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4
; HSA-NEXT: ret void
;
; MESA-LABEL: @array_2xi1_arg(
; MESA-NEXT: entry:
; MESA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to [[ARRAY_2XI1_ARG:%.*]] addrspace(4)*
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[ARRAY_2XI1_ARG]], [[ARRAY_2XI1_ARG]] addrspace(4)* [[TMP1]], i32 0, i32 0
; MESA-NEXT: [[IN_LOAD:%.*]] = load [2 x i1], [2 x i1] addrspace(4)* [[IN_KERNARG_OFFSET]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
; MESA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4
; MESA-NEXT: ret void
;
entry:
%elt0 = extractvalue [2 x i1] %in, 0
%elt1 = extractvalue [2 x i1] %in, 1
store volatile i1 %elt0, i1 addrspace(1)* null, align 4
store volatile i1 %elt1, i1 addrspace(1)* null, align 4
ret void
}
define amdgpu_kernel void @only_empty_struct({} %empty) #0 {
; HSA-LABEL: @only_empty_struct(
; HSA-NEXT: ret void
;
; MESA-LABEL: @only_empty_struct(
; MESA-NEXT: [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(36) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP2:%.*]] = bitcast i8 addrspace(4)* [[TMP1]] to [[ONLY_EMPTY_STRUCT:%.*]] addrspace(4)*
; MESA-NEXT: ret void
;
ret void
}
define amdgpu_kernel void @empty_struct_with_other({} %empty, i32 %arg1) #0 {
; HSA-LABEL: @empty_struct_with_other(
; HSA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]] to [[EMPTY_STRUCT_WITH_OTHER:%.*]] addrspace(4)*
; HSA-NEXT: [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[EMPTY_STRUCT_WITH_OTHER]], [[EMPTY_STRUCT_WITH_OTHER]] addrspace(4)* [[TMP1]], i32 0, i32 1
; HSA-NEXT: [[ARG1_LOAD:%.*]] = load i32, i32 addrspace(4)* [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load !0
; HSA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef
; HSA-NEXT: ret void
;
; MESA-LABEL: @empty_struct_with_other(
; MESA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP2:%.*]] = bitcast i8 addrspace(4)* [[TMP1]] to [[EMPTY_STRUCT_WITH_OTHER:%.*]] addrspace(4)*
; MESA-NEXT: [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds [[EMPTY_STRUCT_WITH_OTHER]], [[EMPTY_STRUCT_WITH_OTHER]] addrspace(4)* [[TMP2]], i32 0, i32 1
; MESA-NEXT: [[ARG1_LOAD:%.*]] = load i32, i32 addrspace(4)* [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load !0
; MESA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef
; MESA-NEXT: ret void
;
store i32 %arg1, i32 addrspace(1)* undef
ret void
}
attributes #0 = { nounwind "target-cpu"="kaveri" } attributes #0 = { nounwind "target-cpu"="kaveri" }
attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" } attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" }
attributes #2 = { nounwind "target-cpu"="tahiti" } attributes #2 = { nounwind "target-cpu"="tahiti" }
; HSA: 0 = !{} ; HSA: 0 = !{}
; HSA: !1 = !{i64 42} ; HSA: !1 = !{i64 42}
; HSA: !2 = !{i64 128} ; HSA: !2 = !{i64 128}
; HSA: !3 = !{i64 1024} ; HSA: !3 = !{i64 1024}
Show All 10 Lines