[AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns.

[LukeGeeson]

Summary

Refactor rL334488 Codegen support: there were instructions with the same encoding, and these duplicates have been removed. In addition, codegen has been improved by better matching of i16 values that these intrinsics take as arguments. For this we had to teach EXTRACT_SUBREG and INSERT_SUBREG which uses AArch64RegisterInfo class hook getSubClassWithSubReg that H-registers can be extracted from the FPR32 and FPR64 register classes.

[SjoerdMeijer]

Thanks for fixing this!

Can you please make the commit message (and the description of this ticket) more descriptive by clearly stating the problem, which is something along the lines of:

"Refactor rL334488 Codegen support: there were instructions with the same encoding, and these duplicates have been removed. In addition, codegen has been improved by better matching of i16 values that these intrinsics take as arguments. For this we had to teach EXTRACT_SUBREG which uses TargetRegisterClass hook getSubClassWithSubReg that H-registers can be extracted from the FPR32 and FPR64 register classes"

lib/Target/AArch64/AArch64InstrInfo.td

4944

I see what you've done here, but I am not sure this comment on itself will be very clear. I think just omitting it is clearer.

lib/Target/AArch64/AArch64RegisterInfo.cpp

78

What is this comment about?

[LukeGeeson]

lib/Target/AArch64/AArch64InstrInfo.td

4944

Removed.

lib/Target/AArch64/AArch64RegisterInfo.cpp

78

A side effect, renamed/removed.

[SjoerdMeijer]

Looks OK to me

lib/Target/AArch64/AArch64InstrFormats.td

   let Inst{10}    = 1;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rd;
 }
 
 
 multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
   let Predicates = [HasNEON, HasFullFP16] in {
-  def HSr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
-                                FPR16, FPR32, vecshiftR16, asm, []> {
-    let Inst{19-16} = imm{3-0};
-    let Inst{23-22} = 0b11;
-  }
-  def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
-                                FPR32, FPR16, vecshiftR32, asm, []> {
-    let Inst{19-16} = imm{3-0};
-    let Inst{22-21} = 0b01;
-  }
-  def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
-                                FPR16, FPR64, vecshiftR32, asm, []> {
-    let Inst{21-16} = imm{5-0};
-    let Inst{23-22} = 0b11;
-  }
-  def DHr : BaseSIMDScalarShift<U, opc, {1,1,1,?,?,?,?},
-                                FPR64, FPR16, vecshiftR64, asm, []> {
-    let Inst{21-16} = imm{5-0};
-    let Inst{23-22} = 0b01;
-    let Inst{31} = 1;
-  }
   def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
                               FPR16, FPR16, vecshiftR16, asm, []> {
     let Inst{19-16} = imm{3-0};
   }
   } // Predicates = [HasNEON, HasFullFP16]
   def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
                               FPR32, FPR32, vecshiftR32, asm, []> {
     let Inst{20-16} = imm{4-0};

lib/Target/AArch64/AArch64InstrInfo.td

 //----------------------------------------------------------------------------
 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
 defm SCVTF  : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
 defm UCVTF  : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
 // Codegen patterns for the above. We don't put these directly on the
 // instructions because TableGen's type inference can't handle the truth.
 // Having the same base pattern for fp <--> int totally freaks it out.
+// Split these patterns into a separate pattern
+
 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
           (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
           (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
           (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
           (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
                                             vecshiftR64:$imm)),
           (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
                                             vecshiftR64:$imm)),
           (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
-def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
-          (FCVTZSHDr (i64 FPR64:$Rn), vecshiftR32:$imm)>;
-def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu FPR16:$Rn, vecshiftR32:$imm)),
-          (FCVTZUSHr FPR16:$Rn, vecshiftR32:$imm)>;
-def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs FPR16:$Rn, vecshiftR32:$imm)),
-          (FCVTZSSHr FPR16:$Rn, vecshiftR32:$imm)>;
-def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),
-          (FCVTZSDHr (f16 FPR16:$Rn), vecshiftR64:$imm)>;
-def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
-          (UCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
           (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
           (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
                                             vecshiftR64:$imm)),
           (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
-def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
-          (SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
-def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR16:$imm)),
-          (SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
           (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
                                             vecshiftR64:$imm)),
           (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
           (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
 
+// Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported.
+
+def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)),
+          (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
+          (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
+          (SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
+            (and FPR32:$Rn, (i32 65535)),
+            vecshiftR16:$imm)),
+          (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
+          (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
+          (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
+def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FCVTZSh FPR16:$Rn, vecshiftR32:$imm),
+            hsub))>;
+def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),
+          (i64 (INSERT_SUBREG
+            (i64 (IMPLICIT_DEF)),
+            (FCVTZSh FPR16:$Rn, vecshiftR64:$imm),
+            hsub))>;
+def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FCVTZUh FPR16:$Rn, vecshiftR32:$imm),
+            hsub))>;
+def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)),
+          (i64 (INSERT_SUBREG
+            (i64 (IMPLICIT_DEF)),
+            (FCVTZUh FPR16:$Rn, vecshiftR64:$imm),
+            hsub))>;
+
 defm SHL      : SIMDScalarLShiftD<   0, 0b01010, "shl", AArch64vshl>;
 defm SLI      : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
 defm SQRSHRN  : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
                                      int_aarch64_neon_sqrshrn>;
 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
                                      int_aarch64_neon_sqrshrun>;
 defm SQSHLU   : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
 defm SQSHL    : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;

lib/Target/AArch64/AArch64RegisterInfo.h

public:
 
   unsigned getCSRFirstUseCost() const override {
     // The cost will be compared against BlockFrequency where entry has the
     // value of 1 << 14. A value of 5 will choose to spill or split really
     // cold path instead of using a callee-saved register.
     return 5;
   }
 
+  const TargetRegisterClass *
+  getSubClassWithSubReg(const TargetRegisterClass *RC,
+                        unsigned Idx) const override;
+
   // Calls involved in thread-local variable lookup save more registers than
   // normal calls, so they need a different mask to represent this.
   const uint32_t *getTLSCallPreservedMask() const;
 
   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
   /// case that 'returned' is on an i64 first argument if the calling convention
   /// is one that can (partially) model this attribute with a preserved mask
   /// (i.e. it is a calling convention that uses the same register for the first

lib/Target/AArch64/AArch64RegisterInfo.cpp

const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
     const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
     return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
   return nullptr;
 }
 
+const TargetRegisterClass *
+AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
+                                       unsigned Idx) const {
+  // The sub_8bit sub-register index is more constrained in 32-bit mode.
+  // It behaves just like the sub_8bit_hi index.
+  if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
+    return &AArch64::FPR32RegClass;
+  else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
+    return &AArch64::FPR64RegClass;
+
+  // Forward to TableGen's default version.
+  return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
+}
+
 const uint32_t *
 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                           CallingConv::ID CC) const {
   bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
   if (CC == CallingConv::GHC)
     // This is academic because all GHC calls are (supposed to be) tail calls
     return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask;
   if (CC == CallingConv::AnyReg)

test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll

 declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64, i32) #1
 declare i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half, i32) #1
 declare i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half, i32) #1
 declare half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32, i32) #1
 declare i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half, i32) #1
 
 define dso_local half @test_vcvth_n_f16_s16_1(i16 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s16_1:
-; CHECK:         sxth w[[wReg:[0-9]+]], w0
-; CHECK-NEXT:    fmov s0, w[[wReg:[0-9]+]]
-; CHECK-NEXT:    scvtf h0, s0, #1
+; CHECK:         fmov s0, w[[wReg:[0-9]+]]
+; CHECK-NEXT:    scvtf h0, h0, #1
 ; CHECK-NEXT:    ret
 entry:
   %sext = sext i16 %a to i32
   %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)
   ret half %fcvth_n
 }
 
 define dso_local half @test_vcvth_n_f16_s16_16(i16 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s16_16:
-; CHECK:         sxth w[[wReg:[0-9]+]], w0
-; CHECK-NEXT:    fmov s0, w[[wReg:[0-9]+]]
-; CHECK-NEXT:    scvtf h0, s0, #16
+; CHECK:         fmov s0, w[[wReg:[0-9]+]]
+; CHECK-NEXT:    scvtf h0, h0, #16
 ; CHECK-NEXT:    ret
 entry:
   %sext = sext i16 %a to i32
   %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 16)
   ret half %fcvth_n
 }
 
 define dso_local half @test_vcvth_n_f16_s32_1(i32 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s32_1:
 ; CHECK:         fmov s0, w0
-; CHECK-NEXT:    scvtf h0, s0, #1
+; CHECK-NEXT:    scvtf h0, h0, #1
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 1)
   ret half %vcvth_n_f16_s32
 }
 
 define dso_local half @test_vcvth_n_f16_s32_16(i32 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s32_16:
 ; CHECK:         fmov s0, w0
-; CHECK-NEXT:    scvtf h0, s0, #16
+; CHECK-NEXT:    scvtf h0, h0, #16
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 16)
   ret half %vcvth_n_f16_s32
 }
 
 define dso_local half @test_vcvth_n_f16_s64_1(i64 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s64_1:
 ; CHECK:         fmov d0, x0
-; CHECK-NEXT:    fcvtzs h0, d0, #1
+; CHECK-NEXT:    scvtf h0, h0, #1
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 1)
   ret half %vcvth_n_f16_s64
 }
 
 define dso_local half @test_vcvth_n_f16_s64_16(i64 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_s64_16:
 ; CHECK:         fmov d0, x0
-; CHECK-NEXT:    fcvtzs h0, d0, #16
+; CHECK-NEXT:    scvtf h0, h0, #16
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
   ret half %vcvth_n_f16_s64
 }
 
 define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s16_f16_1:
-; CHECK:         fcvtzs s0, h0, #1
+; CHECK:         fcvtzs h0, h0, #1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
   %0 = trunc i32 %fcvth_n to i16
   ret i16 %0
 }
 
 define dso_local i16 @test_vcvth_n_s16_f16_16(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s16_f16_16:
-; CHECK:         fcvtzs s0, h0, #16
+; CHECK:         fcvtzs h0, h0, #16
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
   %0 = trunc i32 %fcvth_n to i16
   ret i16 %0
 }
 
 define dso_local i32 @test_vcvth_n_s32_f16_1(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s32_f16_1:
-; CHECK:         fcvtzs s0, h0, #1
+; CHECK:         fcvtzs h0, h0, #1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
   ret i32 %vcvth_n_s32_f16
 }
 
 define dso_local i32 @test_vcvth_n_s32_f16_16(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s32_f16_16:
-; CHECK:         fcvtzs s0, h0, #16
+; CHECK:         fcvtzs h0, h0, #16
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
   ret i32 %vcvth_n_s32_f16
 }
 
 define dso_local i64 @test_vcvth_n_s64_f16_1(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s64_f16_1:
-; CHECK:         fcvtzs d0, h0, #1
+; CHECK:         fcvtzs h0, h0, #1
 ; CHECK-NEXT:    fmov x0, d0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 1)
   ret i64 %vcvth_n_s64_f16
 }
 
 define dso_local i64 @test_vcvth_n_s64_f16_32(half %a) {
 ; CHECK-LABEL: test_vcvth_n_s64_f16_32:
-; CHECK:         fcvtzs d0, h0, #32
+; CHECK:         fcvtzs h0, h0, #32
 ; CHECK-NEXT:    fmov x0, d0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 32)
   ret i64 %vcvth_n_s64_f16
 }
 
 define dso_local half @test_vcvth_n_f16_u16_1(i16 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_u16_1:
-; CHECK:         and w[[wReg:[0-9]+]], w0, #0xffff
-; CHECK-NEXT:    fmov s0, w[[wReg:[0-9]+]]
-; CHECK-NEXT:    ucvtf h0, s0, #1
+; CHECK:         ucvtf h0, h0, #1
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i16 %a to i32
   %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 1)
   ret half %fcvth_n
 }
 
 define dso_local half @test_vcvth_n_f16_u16_16(i16 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_u16_16:
-; CHECK:         and w[[wReg:[0-9]+]], w0, #0xffff
-; CHECK-NEXT:    fmov s0, w[[wReg:[0-9]+]]
-; CHECK-NEXT:    ucvtf h0, s0, #16
+; CHECK:         ucvtf h0, h0, #16
 ; CHECK-NEXT:    ret
 entry:
   %0 = zext i16 %a to i32
   %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 16)
   ret half %fcvth_n
 }
 
 define dso_local half @test_vcvth_n_f16_u32_1(i32 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_u32_1:
 ; CHECK:         fmov s0, w0
-; CHECK-NEXT:    ucvtf h0, s0, #1
+; CHECK-NEXT:    ucvtf h0, h0, #1
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 1)
   ret half %vcvth_n_f16_u32
 }
 
 define dso_local half @test_vcvth_n_f16_u32_16(i32 %a) {
 ; CHECK-LABEL: test_vcvth_n_f16_u32_16:
-; CHECK:         fmov s0, w0
-; CHECK-NEXT:    ucvtf h0, s0, #16
+; CHECK:         ucvtf h0, h0, #16
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 16)
   ret half %vcvth_n_f16_u32
 }
 
 define dso_local i16 @test_vcvth_n_u16_f16_1(half %a) {
 ; CHECK-LABEL: test_vcvth_n_u16_f16_1:
-; CHECK:         fcvtzu s0, h0, #1
+; CHECK:         fcvtzu h0, h0, #1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
   %0 = trunc i32 %fcvth_n to i16
   ret i16 %0
 }
 
 define dso_local i16 @test_vcvth_n_u16_f16_16(half %a) {
 ; CHECK-LABEL: test_vcvth_n_u16_f16_16:
-; CHECK:         fcvtzu s0, h0, #16
+; CHECK:         fcvtzu h0, h0, #16
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
   %0 = trunc i32 %fcvth_n to i16
   ret i16 %0
 }
 
 define dso_local i32 @test_vcvth_n_u32_f16_1(half %a) {
 ; CHECK-LABEL: test_vcvth_n_u32_f16_1:
-; CHECK:         fcvtzu s0, h0, #1
+; CHECK:         fcvtzu h0, h0, #1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
   ret i32 %vcvth_n_u32_f16
 }
 
 define dso_local i32 @test_vcvth_n_u32_f16_16(half %a) {
 ; CHECK-LABEL: test_vcvth_n_u32_f16_16:
-; CHECK:         fcvtzu s0, h0, #16
+; CHECK:         fcvtzu h0, h0, #16
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
   ret i32 %vcvth_n_u32_f16
 }