Add support for scalarizing cttz_zero_undef

[petarj]

Summary

Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.

[arsenm]

The actual patch part is obvious. The test looks overly strict, with the specific registers used for each instruction

[petarj]

I have loosened up the restrictions in the test case.
PTAL.

[arsenm]

LGTM

[petarj]

Closed by commit rL215330 (authored by @petarj).

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::ANY_EXTEND:
   case ISD::BSWAP:
   case ISD::CTLZ:
   case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
+  case ISD::CTTZ_ZERO_UNDEF:
   case ISD::FABS:
   case ISD::FCEIL:
   case ISD::FCOS:
   case ISD::FEXP:
   case ISD::FEXP2:
   case ISD::FFLOOR:
   case ISD::FLOG:
   case ISD::FLOG10:

test/CodeGen/Mips/cttz-v.ll

+; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+
+declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
+
+define <2 x i32> @cttzv2i32(<2 x i32> %x) {
+entry:
+; MIPS32-DAG: addiu   $[[R0:[0-9]+]], $4, -1
+; MIPS32-DAG: not     $[[R1:[0-9]+]], $4
+; MIPS32-DAG: and     $[[R2:[0-9]+]], $[[R1]], $[[R0]]
+; MIPS32-DAG: clz     $[[R3:[0-9]+]], $[[R2]]
+; MIPS32-DAG: addiu   $[[R4:[0-9]+]], $zero, 32
+; MIPS32-DAG: subu    $2, $[[R4]], $[[R3]]
+; MIPS32-DAG: addiu   $[[R5:[0-9]+]], $5, -1
+; MIPS32-DAG: not     $[[R6:[0-9]+]], $5
+; MIPS32-DAG: and     $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MIPS32-DAG: clz     $[[R8:[0-9]+]], $[[R7]]
+; MIPS32-DAG: jr      $ra
+; MIPS32-DAG: subu    $3, $[[R4]], $[[R8]]
+
+; MIPS64-DAG: addiu   $[[R0:[0-9]+]], $4, -1
+; MIPS64-DAG: not     $[[R1:[0-9]+]], $4
+; MIPS64-DAG: and     $[[R2:[0-9]+]], $[[R1]], $[[R0]]
+; MIPS64-DAG: clz     $[[R3:[0-9]+]], $[[R2]]
+; MIPS64-DAG: addiu   $[[R4:[0-9]+]], $zero, 32
+; MIPS64-DAG: subu    $2, $[[R4]], $[[R3]]
+; MIPS64-DAG: addiu   $[[R5:[0-9]+]], $5, -1
+; MIPS64-DAG: not     $[[R6:[0-9]+]], $5
+; MIPS64-DAG: and     $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MIPS64-DAG: clz     $[[R8:[0-9]+]], $[[R7]]
+; MIPS64-DAG: jr      $ra
+; MIPS64-DAG: subu    $3, $[[R4]], $[[R8]]
+
+  %ret = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true)
+  ret <2 x i32> %ret
+}
+