[Docs] Add the missing documentation for expandload and compressstore intrinsics

[craig.topper]

Summary

These intrinsics have been avaible in llvm for a few years and are implemented by the X86 target for AVX512. But it looks like they were never documented.

We may also be missing scalarization support on targets that don't support them. And I think we probably handle them incorrectly in type legalization.

[delena]

I tried to add documentation a while ago https://reviews.llvm.org/D26743

[craig.topper]

Abandoning in favor of Elena's more detailed documentation.

docs/LangRef.rst

 ::
 
        %res = call <16 x float> @llvm.masked.load.v16f32.p0v16f32 (<16 x float>* %ptr, i32 4, <16 x i1>%mask, <16 x float> %passthru)
 
        ;; The result of the two following instructions is identical aside from potential memory access exception
        %loadlal = load <16 x float>, <16 x float>* %ptr, align 4
        %res = select <16 x i1> %mask, <16 x float> %loadlal, <16 x float> %passthru
 
+.. _int_mexpandload:
+
+'``llvm.masked.expandload.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic. The loaded data is a vector of any integer, floating-point or pointer data type.
+
+::
+
+      declare <16 x float>  @llvm.masked.expandload.v16f32(float* <ptr>, <16 x i1> <mask>, <16 x float> <passthru>)
+      declare <2 x double>  @llvm.masked.expandload.v2f64(double* <ptr>, <2 x i1>  <mask>, <2 x double> <passthru>)
+
+Overview:
+"""""""""
+
+Reads contiguous values from memory to sparse elements in the result vector selected by the provided mask. The masked-off lanes in the result vector are taken from the corresponding lanes of the '``passthru``' operand.
+
+
+Arguments:
+""""""""""
+
+The first operand is the base pointer for the load. The second operand, mask, is a vector of boolean values with the same number of elements as the return type. The fourth is a pass-through value that is used to fill the masked-off lanes of the result. The return type and the type of the '``passthru``' operand are the same vector types. The pointer type is the element type of the vector.
+
+
+Semantics:
+""""""""""
+
+The '``llvm.masked.expandload``' intrinsic is designed for conditional expansion of vector elements from memory in a single IR operation. It is useful for targets that support expanding vector masked loads. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar load operations.
+
 .. _int_mstore:
 
 '``llvm.masked.store.*``' Intrinsics
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 This is an overloaded intrinsic. The data stored in memory is a vector of any integer, floating-point or pointer data type.
::
 
        call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %value, <16 x float>* %ptr, i32 4,  <16 x i1> %mask)
 
        ;; The result of the following instructions is identical aside from potential data races and memory access exceptions
        %oldval = load <16 x float>, <16 x float>* %ptr, align 4
        %res = select <16 x i1> %mask, <16 x float> %value, <16 x float> %oldval
        store <16 x float> %res, <16 x float>* %ptr, align 4
 
+.. _int_mcompressstore:
+
+'``llvm.masked.compressstore.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic. The data stored in memory is a vector of any integer, floating-point or pointer data type.
+
+::
+
+       declare void @llvm.masked.compressstore.v8i32(<8  x i32> <value>, i32* <ptr>, <8  x i1> <mask>)
+       declare void @llvm.masked.compressstore.v16f32(<16 x float> <value>, float* <ptr>, <16 x i1> <mask>)
+
+Overview:
+"""""""""
+
+Writes contiguous memory according by compressing source elements according to the provided mask. The mask holds a bit for each vector lane. If the mask bit is not set that element will not be written to memory.
+
+Arguments:
+""""""""""
+
+The first operand is the vector value to be written to memory. The second operand is the base pointer for the store, its type is the element type of the value operand. The third operand, mask, is a vector of boolean values. The types of the mask and the value operand must have the same number of vector elements.
+
+
+Semantics:
+""""""""""
+
+The '``llvm.masked.compressstore``' intrinsics is designed for conditional writing of selected vector elements in a single IR operation. It is useful for targets that support vector masked compressed store. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar store operations.
 
 Masked Vector Gather and Scatter Intrinsics
 -------------------------------------------
 
 LLVM provides intrinsics for vector gather and scatter operations. They are similar to :ref:`Masked Vector Load and Store <int_mload_mstore>`, except they are designed for arbitrary memory accesses, rather than sequential memory accesses. Gather and scatter also employ a mask operand, which holds one bit per vector element, switching the associated vector lane on or off. The memory addresses corresponding to the "off" lanes are not accessed. When all bits are off, no memory is accessed.
 
 .. _int_mgather: