[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions

[atanasyan]

Summary

The MipsAsmParser::loadImmediate can load immediates of various sizes into a register. Idea of this change is to use loadImmediate in the MipsAsmParser::expandMemInst method to load offset into a register and then call required load/store instruction.

The patch removes separate expandLoadInst and expandStoreInst methods and does everything in the expandMemInst method to escape code duplication.

[smaksimovic]

LGTM.

test/MC/Mips/mips64-expansions.s

273

Minor nit: ... with offsets exceeding 16 bits in size.

[atanasyan]

Thanks for review.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
                          const MCSubtargetInfo *STI);
 
   bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                   const MCSubtargetInfo *STI);
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                      const MCSubtargetInfo *STI, bool IsLoad);
 
-  void expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
-                      const MCSubtargetInfo *STI);
-
-  void expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
-                       const MCSubtargetInfo *STI);
-
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                const MCSubtargetInfo *STI);
 
   bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                             const MCSubtargetInfo *STI);
 
   bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                        const MCSubtargetInfo *STI);
bool isMemWithSimmOffset() const {
     return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
   }
 
   bool isMemWithPtrSizeOffset() const {
     if (!isMem())
       return false;
     if (!getMemBase()->isGPRAsmReg())
       return false;
-    const unsigned PtrBits = 32;
+    const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32;
     if (isa<MCTargetExpr>(getMemOff()) ||
         (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
       return true;
     MCValue Res;
     bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
     return IsReloc && isIntN(PtrBits, Res.getConstant());
   }
 
if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
     for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
       const MCOperandInfo &OpInfo = MCID.OpInfo[i];
       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
         MCOperand &Op = Inst.getOperand(i);
         if (Op.isImm()) {
-          int MemOffset = Op.getImm();
+          int64_t MemOffset = Op.getImm();
           if (MemOffset < -32768 || MemOffset > 32767) {
             // Offset can't exceed 16bit value.
             expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
             return getParser().hasPendingError();
           }
         } else if (Op.isExpr()) {
           const MCExpr *Expr = Op.getExpr();
           if (Expr->getKind() == MCExpr::SymbolRef) {
if (ImmValue == 0) {
     } else
       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
   }
   return false;
 }
 
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                   const MCSubtargetInfo *STI, bool IsLoad) {
-  if (IsLoad)
-    expandLoadInst(Inst, IDLoc, Out, STI);
-  else
-    expandStoreInst(Inst, IDLoc, Out, STI);
-}
-
-void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
-                                   const MCSubtargetInfo *STI) {
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
   const MCOperand &BaseRegOp = Inst.getOperand(1);
   assert(BaseRegOp.isReg() && "expected register operand kind");
   const MCOperand &OffsetOp = Inst.getOperand(2);
 
   MipsTargetStreamer &TOut = getTargetStreamer();
   unsigned DstReg = DstRegOp.getReg();
   unsigned BaseReg = BaseRegOp.getReg();
   unsigned TmpReg = DstReg;
 
   const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
   int16_t DstRegClass = Desc.OpInfo[0].RegClass;
   unsigned DstRegClassID =
       getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
                (DstRegClassID == Mips::GPR64RegClassID);
 
-  if (!IsGPR || (BaseReg == DstReg)) {
+  if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
     // At this point we need AT to perform the expansions
     // and we exit if it is not available.
     TmpReg = getATReg(IDLoc);
     if (!TmpReg)
       return;
   }
 
   if (OffsetOp.isImm()) {
-    TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
-                               OffsetOp.getImm(), TmpReg, IDLoc, STI);
-  } else {
-    assert(OffsetOp.isExpr() && "expected expression operand kind");
-    const MCExpr *ExprOffset = OffsetOp.getExpr();
-    MCOperand LoOperand = MCOperand::createExpr(
-        MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
-    MCOperand HiOperand = MCOperand::createExpr(
-        MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
-    TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
-                               LoOperand, TmpReg, IDLoc, STI);
-  }
-}
+    int64_t LoOffset = OffsetOp.getImm() & 0xffff;
+    int64_t HiOffset = OffsetOp.getImm() & ~0xffff;
 
-void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
-                                    const MCSubtargetInfo *STI) {
-  const MCOperand &SrcRegOp = Inst.getOperand(0);
-  assert(SrcRegOp.isReg() && "expected register operand kind");
-  const MCOperand &BaseRegOp = Inst.getOperand(1);
-  assert(BaseRegOp.isReg() && "expected register operand kind");
-  const MCOperand &OffsetOp = Inst.getOperand(2);
+    // If msb of LoOffset is 1(negative number) we must increment
+    // HiOffset to account for the sign-extension of the low part.
+    if (LoOffset & 0x8000)
+      HiOffset += 0x10000;
 
-  MipsTargetStreamer &TOut = getTargetStreamer();
-  unsigned SrcReg = SrcRegOp.getReg();
-  unsigned BaseReg = BaseRegOp.getReg();
+    bool IsLargeOffset = HiOffset != 0;
 
-  if (OffsetOp.isImm()) {
-    TOut.emitStoreWithImmOffset(Inst.getOpcode(), SrcReg, BaseReg,
-                                OffsetOp.getImm(),
-                                [&]() { return getATReg(IDLoc); }, IDLoc, STI);
+    if (IsLargeOffset) {
+      bool Is32BitImm = (HiOffset >> 32) == 0;
+      if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
+                        IDLoc, Out, STI))
         return;
     }
 
-  unsigned ATReg = getATReg(IDLoc);
-  if (!ATReg)
-    return;
-
+    if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
+      TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
+                   BaseReg, IDLoc, STI);
+    TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
+  } else {
     assert(OffsetOp.isExpr() && "expected expression operand kind");
     const MCExpr *ExprOffset = OffsetOp.getExpr();
     MCOperand LoOperand = MCOperand::createExpr(
         MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
     MCOperand HiOperand = MCOperand::createExpr(
         MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
-  TOut.emitStoreWithSymOffset(Inst.getOpcode(), SrcReg, BaseReg, HiOperand,
-                              LoOperand, ATReg, IDLoc, STI);
+
+    if (IsLoad)
+      TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
+                                 LoOperand, TmpReg, IDLoc, STI);
+    else
+      TOut.emitStoreWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
+                                  LoOperand, TmpReg, IDLoc, STI);
+  }
 }
 
 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                             MCStreamer &Out,
                                             const MCSubtargetInfo *STI) {
   unsigned OpNum = Inst.getNumOperands();
   unsigned Opcode = Inst.getOpcode();
   unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;

test/MC/Mips/mips64-expansions.s

 # CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
 # CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
 # CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
 # CHECK: ori   $1, $1, 65535  # encoding: [0xff,0xff,0x21,0x34]
 # CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
 # CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
 # CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
 
-# Test ld/sd/lld with offsets exceed 16-bit size.
+# Test lb/sb/ld/sd/lld with offsets exceed 16-bit size.
 
     ld  $4, 0x8000
 # CHECK:      lui     $4, 1
-# CHECK-NEXT: addu    $4, $4, $zero
 # CHECK-NEXT: ld      $4, -32768($4)
 
     ld  $4, 0x20008($3)
 # CHECK:      lui     $4, 2
 # CHECK-NEXT: addu    $4, $4, $3
 # CHECK-NEXT: ld      $4, 8($4)
 
+    ld  $4,0x100010004
+# CHECK:      addiu   $4, $zero, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ld      $4, 4($4)
+
+    ld  $4,0x1800180018004
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ld      $4, -32764($4)
+
+    ld  $4,0x1800180018004($3)
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: daddu   $4, $4, $3
+# CHECK-NEXT: ld      $4, -32764($4)
+
     sd  $4, 0x8000
 # CHECK:      lui     $1, 1
-# CHECK-NEXT: addu    $1, $1, $zero
 # CHECK-NEXT: sd      $4, -32768($1)
 
     sd  $4, 0x20008($3)
 # CHECK:      lui     $1, 2
 # CHECK-NEXT: addu    $1, $1, $3
 # CHECK-NEXT: sd      $4, 8($1)
 
+    sd  $4,0x100010004
+# CHECK:      addiu   $1, $zero, 1
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 1
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: sd      $4, 4($1)
+
+    sd  $4,0x1800180018004
+# CHECK:      lui     $1, 1
+# CHECK-NEXT: ori     $1, $1, 32769
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 32770
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: sd      $4, -32764($1)
+
+    sd  $4,0x1800180018004($3)
+# CHECK:      lui     $1, 1
+# CHECK-NEXT: ori     $1, $1, 32769
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 32770
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: daddu   $1, $1, $3
+# CHECK-NEXT: sd      $4, -32764($1)
+
     lld $4, 0x8000
 # CHECK:      lui     $4, 1
-# CHECK-NEXT: addu    $4, $4, $zero
 # CHECK-NEXT: lld     $4, -32768($4)
 
     lld $4, 0x20008($3)
 # CHECK:      lui     $4, 2
 # CHECK-NEXT: addu    $4, $4, $3
 # CHECK-NEXT: lld     $4, 8($4)
+
+    lld $4,0x100010004
+# CHECK:      addiu   $4, $zero, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lld     $4, 4($4)
+
+    lld $4,0x1800180018004
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lld     $4, -32764($4)
+
+    lld $4,0x1800180018004($3)
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: daddu   $4, $4, $3
+# CHECK-NEXT: lld     $4, -32764($4)
+
+    lb  $4,0x100010004
+# CHECK:      addiu   $4, $zero, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lb      $4, 4($4)
+
+    lb  $4,0x1800180018004
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lb      $4, -32764($4)
+
+    lb  $4,0x1800180018004($3)
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: daddu   $4, $4, $3
+# CHECK-NEXT: lb      $4, -32764($4)
+
+    sb  $4,0x100010004
+# CHECK:      addiu   $1, $zero, 1
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 1
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: sb      $4, 4($1)
+
+    sb  $4,0x1800180018004
+# CHECK:      lui     $1, 1
+# CHECK-NEXT: ori     $1, $1, 32769
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 32770
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: sb      $4, -32764($1)
+
+    sb  $4,0x1800180018004($3)
+# CHECK:      lui     $1, 1
+# CHECK-NEXT: ori     $1, $1, 32769
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: ori     $1, $1, 32770
+# CHECK-NEXT: dsll    $1, $1, 16
+# CHECK-NEXT: daddu   $1, $1, $3
+# CHECK-NEXT: sb      $4, -32764($1)
+
+    lh  $4,0x100010004
+# CHECK:      addiu   $4, $zero, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lh      $4, 4($4)
+
+    lh  $4,0x1800180018004
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lh      $4, -32764($4)
+
+    lh  $4,0x1800180018004($3)
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: daddu   $4, $4, $3
+# CHECK-NEXT: lh      $4, -32764($4)
+
+    lhu $4,0x100010004
+# CHECK:      addiu   $4, $zero, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 1
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lhu     $4, 4($4)
+
+    lhu $4,0x1800180018004
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: lhu     $4, -32764($4)
+
+    lhu $4,0x1800180018004($3)
+# CHECK:      lui     $4, 1
+# CHECK-NEXT: ori     $4, $4, 32769
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: ori     $4, $4, 32770
+# CHECK-NEXT: dsll    $4, $4, 16
+# CHECK-NEXT: daddu   $4, $4, $3
+# CHECK-NEXT: lhu     $4, -32764($4)

test/MC/Mips/mips64r5/invalid.s

# RUN: FileCheck %s < %t1
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         dmtc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmtc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         sd $32, 65536($32)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -2147483649($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
-        lb $4, 2147483648($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -2147483649($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
-        lbu $4, 2147483648($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset

test/MC/Mips/mips64r5/valid.s

a:
                                        # CHECK:         #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
         j         1328                 # CHECK: j 1328  # encoding: [0x08,0x00,0x01,0x4c]
         jal       21100                # CHECK: jal 21100     # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
         jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
         l.s       $f2, 8($3)           # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
         l.d       $f2, 8($3)           # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
-        lb        $24,-14515($10)
-        lbu       $8,30195($v1)
-        ld        $sp,-28645($s1)
+        lb        $24,-2147483649($10)
+        lbu       $24,-2147483649($10)
+        ld        $sp,-2147483649($s1)
         ldc1      $f11,16391($s0)
         ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
         ldl       $24,-4167($24)
         ldr       $14,-30358($s4)
         ldxc1     $f8,$s7($15)
-        lh        $11,-8556($s5)
-        lhu       $s3,-22851($v0)
+        lh        $11,-2147483649($s5)
+        lhu       $s3,-2147483649($v0)
         li        $at,-29773
         li        $zero,-29889
         ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
         lld       $zero,-14736($ra)    # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
+        lld       $24,-2147483649($10)
         luxc1     $f19,$s6($s5)
         lw        $8,5674($a1)
         lwc1      $f16,10225($k0)
         lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
         lwl       $s4,-4231($15)
         lwr       $zero,-19147($gp)
         lwu       $s3,-24086($v1)
         lwxc1     $f12,$s1($s8)

test/MC/Mips/mips64r6/invalid.s

.set noat
         lh  $33, 8($4)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhe $34, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhu $35, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhue $36, 8($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lh  $2, 8($34)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhu $4, 8($35)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
-        lh  $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
-        lh  $2, 2147483648($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
         lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
-        lhu $4, 2147483648($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
         lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         blel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bleul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bgel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
.set noat
         lsa     $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         lsa     $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         dmtc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmtc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
-        ld $2, 2147483648($4)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
-        ld  $2, -2147483649($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
         ld $32, 65536($32)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
-        lld  $2, -2147483649($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
-        lld  $2, 2147483648($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
-        sd  $2, -2147483649($4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
         lld $32, 4096($32)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
-        sd  $2, 2147483648($4)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
         sd $32, 65536($32)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         dsrl $2, $4, 64      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
         dsrl $2, $4, -2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
         dsrl $32, $32, 32    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         dsrl32 $2, $4, 32    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
         dsrl32 $32, $32, 32  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         dsrlv $2, $4, 2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         dsrlv $32, $32, $32  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
         lb $32, 8($5)        # CHECK: :[[@LINE]]:12: error: invalid register number
-        lb $4, -2147483649($5)    # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
-        lb $4, 2147483648($5)     # CHECK: :[[@LINE]]:16: error: expected memory with 32-bit signed offset
         lb $4, 8($32)        # CHECK: :[[@LINE]]:18: error: invalid register number
         lbu $32, 8($5)       # CHECK: :[[@LINE]]:13: error: invalid register number
-        lbu $4, -2147483649($5)   # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
-        lbu $4, 2147483648($5)    # CHECK: :[[@LINE]]:17: error: expected memory with 32-bit signed offset
         lbu $4, 8($32)       # CHECK: :[[@LINE]]:19: error: invalid register number
         ldc1 $f32, 300($10)   # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         ldc1 $f7, 300($32)    # CHECK: :[[@LINE]]:23: error: invalid register number
         sdc1 $f32, 64($10)    # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
         sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         sdc1 $f7, 32768($10)  # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset