[llvm-mca] Move DispatchStage::cycleEvent to preExecute. NFC.

[mattd]

Summary

This is an intermediate change, it moves the non-notification logic from
Backend::notifyCycleBegin to runCycle().

Once the scheduler becomes part of the Execution stage
the explicit call to Scheduler::cycleEvent will disappear.

The logic for Dispatch::cycleEvent() can be in
the preExecute phase, which this patch addresses.

[andreadb]

LGTM.

Thanks

llvm/trunk/tools/llvm-mca/Backend.cpp

void Backend::run() {
   while (Fetch->isReady() || !Dispatch->isReady())
     runCycle(Cycles++);
 }
 
 void Backend::runCycle(unsigned Cycle) {
   notifyCycleBegin(Cycle);
 
   InstRef IR;
+  Dispatch->preExecute(IR);
+  HWS->cycleEvent(); // TODO: This will eventually be stage-ified.
+
   while (Fetch->execute(IR)) {
     if (!Dispatch->execute(IR))
       break;
     Fetch->postExecute(IR);
   }
 
   notifyCycleEnd(Cycle);
 }
 
 void Backend::notifyCycleBegin(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
-
-  Dispatch->cycleEvent();
-  HWS->cycleEvent();
 }
 
 void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onInstructionEvent(Event);
 }
 
 void Backend::notifyStallEvent(const HWStallEvent &Event) {

llvm/trunk/tools/llvm-mca/DispatchStage.h

DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), SC(Sched),
         RAT(llvm::make_unique<RegisterFile>(Subtarget.getSchedModel(), MRI,
                                             RegisterFileSize)),
         RCU(llvm::make_unique<RetireControlUnit>(Subtarget.getSchedModel(),
                                                  this)),
         Owner(B), STI(Subtarget) {}
 
-  void cycleEvent() {
-    RCU->cycleEvent();
-    AvailableEntries =
-        CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
-    CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
-  }
-
   virtual bool isReady() const override final { return isRCUEmpty(); }
+  virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
   void notifyInstructionRetired(const InstRef &IR);
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
   void onInstructionExecuted(unsigned TokenID) {
     RCU->onInstructionExecuted(TokenID);
   }
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/DispatchStage.cpp

void DispatchStage::dispatch(InstRef IR) {
   notifyInstructionDispatched(IR, RegisterFiles);
 
   // Now move the instruction into the scheduler's queue.
   // The scheduler is responsible for checking if this is a zero-latency
   // instruction that doesn't consume pipeline/scheduler resources.
   SC->scheduleInstruction(IR);
 }
 
+void DispatchStage::preExecute(const InstRef &IR) {
+  RCU->cycleEvent();
+  AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
+  CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
+}
+
 bool DispatchStage::execute(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   if (!isAvailable(Desc.NumMicroOps) || !canDispatch(IR))
     return false;
   dispatch(IR);
   return true;
 }
 
 #ifndef NDEBUG
 void DispatchStage::dump() const {
   RAT->dump();
   RCU->dump();
 }
 #endif
 } // namespace mca