[Sparc] Add support for 13-bit PIC

[dcederman]

Summary

When compiling with -fpic, in contrast to -fPIC, use only the immediate field to index into the GOT. This saves space if the GOT is known to be small. The linker will warn if the GOT is too large for this method.

[jyknight]

It doesn't look like we can parse the textual asm produced by this. E.g.:

test.s:

ld      [%i0+x], %i0
.common x,4,4

Then running llvm-mc -filetype=obj -position-independent -triple sparc -o test.o test.s hits an assert in SparcMCCodeEmitter::getMachineOpValue at SparcMCCodeEmitter.cpp:152, because it got parsed as a <MCOperand Expr:(x)>, not as a SparcMCExpr with the VK_SPARC_GOT13 kind, as it should.

Same failure, actually, without the -position-independent, too, actually, should've parsed as VK_SPARC_13. But at least we don't ever actually generate that on output.

lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp

61

Strange that this doesn't print %got13. But, checking with gcc and gnu as, they don't support it. So, great, more magic just like %got22, %got10, %pc22, and %pc10.

[dcederman]

In D47136#1106470, @jyknight wrote:

Same failure, actually, without the -position-independent, too, actually, should've parsed as VK_SPARC_13. But at least we don't ever actually generate that on output.

I ran into this problem before and tried to fix it. I will combine that patch with this and add the GOT13 part to the assembler.

[dcederman]

Added support to the assembler so that it can properly parse the output generated by -fpic.

[brad]

ping

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
   case AsmToken::Identifier: {
     StringRef Identifier;
     if (!getParser().parseIdentifier(Identifier)) {
       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
       MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
 
       const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
                                                   getContext());
-      if (isCall && getContext().getObjectFileInfo()->isPositionIndependent())
-        Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
-                                  getContext());
+      SparcMCExpr::VariantKind Kind = SparcMCExpr::VK_Sparc_13;
+
+      if (getContext().getObjectFileInfo()->isPositionIndependent()) {
+        if (isCall)
+          Kind = SparcMCExpr::VK_Sparc_WPLT30;
+        else
+          Kind = SparcMCExpr::VK_Sparc_GOT13;
+      }
+
+      Res = SparcMCExpr::create(Kind, Res, getContext());
+
       Op = SparcOperand::CreateImm(Res, S, E);
     }
     break;
   }
   }
   return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
 }
 

lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   case Sparc::fixup_sparc_pc22:
   case Sparc::fixup_sparc_got22:
   case Sparc::fixup_sparc_tls_gd_hi22:
   case Sparc::fixup_sparc_tls_ldm_hi22:
   case Sparc::fixup_sparc_tls_ie_hi22:
   case Sparc::fixup_sparc_hi22:
     return (Value >> 10) & 0x3fffff;
 
+  case Sparc::fixup_sparc_got13:
+  case Sparc::fixup_sparc_13:
+    return Value & 0x1fff;
+
   case Sparc::fixup_sparc_pc10:
   case Sparc::fixup_sparc_got10:
   case Sparc::fixup_sparc_tls_gd_lo10:
   case Sparc::fixup_sparc_tls_ldm_lo10:
   case Sparc::fixup_sparc_tls_ie_lo10:
   case Sparc::fixup_sparc_lo10:
     return Value & 0x3ff;
 
public:
     const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
       const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_sparc_13",        19,     13,  0 },
         { "fixup_sparc_hi22",      10,     22,  0 },
         { "fixup_sparc_lo10",      22,     10,  0 },
         { "fixup_sparc_h44",       10,     22,  0 },
         { "fixup_sparc_m44",       22,     10,  0 },
         { "fixup_sparc_l44",       20,     12,  0 },
         { "fixup_sparc_hh",        10,     22,  0 },
         { "fixup_sparc_hm",        22,     10,  0 },
         { "fixup_sparc_pc22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_pc10",      22,     10,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_got22",     10,     22,  0 },
         { "fixup_sparc_got10",     22,     10,  0 },
+        { "fixup_sparc_got13",     19,     13,  0 },
         { "fixup_sparc_wplt30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_tls_gd_hi22",   10, 22,  0 },
         { "fixup_sparc_tls_gd_lo10",   22, 10,  0 },
         { "fixup_sparc_tls_gd_add",     0,  0,  0 },
         { "fixup_sparc_tls_gd_call",    0,  0,  0 },
         { "fixup_sparc_tls_ldm_hi22",  10, 22,  0 },
         { "fixup_sparc_tls_ldm_lo10",  22, 10,  0 },
         { "fixup_sparc_tls_ldm_add",    0,  0,  0 },
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
 
       const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_2",    20,      2,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_14",    0,     14,  MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_sparc_13",         0,     13,  0 },
         { "fixup_sparc_hi22",       0,     22,  0 },
         { "fixup_sparc_lo10",       0,     10,  0 },
         { "fixup_sparc_h44",        0,     22,  0 },
         { "fixup_sparc_m44",        0,     10,  0 },
         { "fixup_sparc_l44",        0,     12,  0 },
         { "fixup_sparc_hh",         0,     22,  0 },
         { "fixup_sparc_hm",         0,     10,  0 },
         { "fixup_sparc_pc22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_pc10",       0,     10,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_got22",      0,     22,  0 },
         { "fixup_sparc_got10",      0,     10,  0 },
+        { "fixup_sparc_got13",      0,     13,  0 },
         { "fixup_sparc_wplt30",      0,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_tls_gd_hi22",    0, 22,  0 },
         { "fixup_sparc_tls_gd_lo10",    0, 10,  0 },
         { "fixup_sparc_tls_gd_add",     0,  0,  0 },
         { "fixup_sparc_tls_gd_call",    0,  0,  0 },
         { "fixup_sparc_tls_ldm_hi22",   0, 22,  0 },
         { "fixup_sparc_tls_ldm_lo10",   0, 10,  0 },
         { "fixup_sparc_tls_ldm_add",    0,  0,  0 },

lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

case FK_Data_2:                return ((Fixup.getOffset() % 2)
                                          ? ELF::R_SPARC_UA16
                                          : ELF::R_SPARC_16);
   case FK_Data_4:                return ((Fixup.getOffset() % 4)
                                          ? ELF::R_SPARC_UA32
                                          : ELF::R_SPARC_32);
   case FK_Data_8:                return ((Fixup.getOffset() % 8)
                                          ? ELF::R_SPARC_UA64
                                          : ELF::R_SPARC_64);
+  case Sparc::fixup_sparc_13:    return ELF::R_SPARC_13;
   case Sparc::fixup_sparc_hi22:  return ELF::R_SPARC_HI22;
   case Sparc::fixup_sparc_lo10:  return ELF::R_SPARC_LO10;
   case Sparc::fixup_sparc_h44:   return ELF::R_SPARC_H44;
   case Sparc::fixup_sparc_m44:   return ELF::R_SPARC_M44;
   case Sparc::fixup_sparc_l44:   return ELF::R_SPARC_L44;
   case Sparc::fixup_sparc_hh:    return ELF::R_SPARC_HH22;
   case Sparc::fixup_sparc_hm:    return ELF::R_SPARC_HM10;
   case Sparc::fixup_sparc_got22: return ELF::R_SPARC_GOT22;
   case Sparc::fixup_sparc_got10: return ELF::R_SPARC_GOT10;
+  case Sparc::fixup_sparc_got13: return ELF::R_SPARC_GOT13;
   case Sparc::fixup_sparc_tls_gd_hi22:   return ELF::R_SPARC_TLS_GD_HI22;
   case Sparc::fixup_sparc_tls_gd_lo10:   return ELF::R_SPARC_TLS_GD_LO10;
   case Sparc::fixup_sparc_tls_gd_add:    return ELF::R_SPARC_TLS_GD_ADD;
   case Sparc::fixup_sparc_tls_gd_call:   return ELF::R_SPARC_TLS_GD_CALL;
   case Sparc::fixup_sparc_tls_ldm_hi22:  return ELF::R_SPARC_TLS_LDM_HI22;
   case Sparc::fixup_sparc_tls_ldm_lo10:  return ELF::R_SPARC_TLS_LDM_LO10;
   case Sparc::fixup_sparc_tls_ldm_add:   return ELF::R_SPARC_TLS_LDM_ADD;
   case Sparc::fixup_sparc_tls_ldm_call:  return ELF::R_SPARC_TLS_LDM_CALL;

lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h

enum Fixups {
       /// fixup_sparc_br19 - 19-bit PC relative relocation for
       /// branches on icc/xcc
       fixup_sparc_br19,
 
       /// fixup_sparc_bpr  - 16-bit fixup for bpr
       fixup_sparc_br16_2,
       fixup_sparc_br16_14,
 
+      /// fixup_sparc_13 - 13-bit fixup
+      fixup_sparc_13,
+
       /// fixup_sparc_hi22  - 22-bit fixup corresponding to %hi(foo)
       /// for sethi
       fixup_sparc_hi22,
 
       /// fixup_sparc_lo10  - 10-bit fixup corresponding to %lo(foo)
       fixup_sparc_lo10,
 
       /// fixup_sparc_h44  - 22-bit fixup corresponding to %h44(foo)
enum Fixups {
       fixup_sparc_pc10,
 
       /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo)
       fixup_sparc_got22,
 
       /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo)
       fixup_sparc_got10,
 
+      /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo)
+      fixup_sparc_got13,
+
       /// fixup_sparc_wplt30
       fixup_sparc_wplt30,
 
       /// fixups for Thread Local Storage
       fixup_sparc_tls_gd_hi22,
       fixup_sparc_tls_gd_lo10,
       fixup_sparc_tls_gd_add,
       fixup_sparc_tls_gd_call,

lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h

enum VariantKind {
     VK_Sparc_M44,
     VK_Sparc_L44,
     VK_Sparc_HH,
     VK_Sparc_HM,
     VK_Sparc_PC22,
     VK_Sparc_PC10,
     VK_Sparc_GOT22,
     VK_Sparc_GOT10,
+    VK_Sparc_GOT13,
+    VK_Sparc_13,
     VK_Sparc_WPLT30,
     VK_Sparc_R_DISP32,
     VK_Sparc_TLS_GD_HI22,
     VK_Sparc_TLS_GD_LO10,
     VK_Sparc_TLS_GD_ADD,
     VK_Sparc_TLS_GD_CALL,
     VK_Sparc_TLS_LDM_HI22,
     VK_Sparc_TLS_LDM_LO10,

lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp

bool SparcMCExpr::printVariantKind(raw_ostream &OS, VariantKind Kind)
   case VK_Sparc_HH:       OS << "%hh(";  break;
   case VK_Sparc_HM:       OS << "%hm(";  break;
     // FIXME: use %pc22/%pc10, if system assembler supports them.
   case VK_Sparc_PC22:     OS << "%hi("; break;
   case VK_Sparc_PC10:     OS << "%lo("; break;
     // FIXME: use %got22/%got10, if system assembler supports them.
   case VK_Sparc_GOT22:    OS << "%hi("; break;
   case VK_Sparc_GOT10:    OS << "%lo("; break;
+  case VK_Sparc_GOT13:    closeParen = false; break;
+  case VK_Sparc_13:       closeParen = false; break;
   case VK_Sparc_WPLT30:   closeParen = false; break;
   case VK_Sparc_R_DISP32: OS << "%r_disp32("; break;
   case VK_Sparc_TLS_GD_HI22:   OS << "%tgd_hi22(";   break;
   case VK_Sparc_TLS_GD_LO10:   OS << "%tgd_lo10(";   break;
   case VK_Sparc_TLS_GD_ADD:    OS << "%tgd_add(";    break;
   case VK_Sparc_TLS_GD_CALL:   OS << "%tgd_call(";   break;
   case VK_Sparc_TLS_LDM_HI22:  OS << "%tldm_hi22(";  break;
   case VK_Sparc_TLS_LDM_LO10:  OS << "%tldm_lo10(";  break;
return StringSwitch<SparcMCExpr::VariantKind>(name)
     .Case("m44", VK_Sparc_M44)
     .Case("l44", VK_Sparc_L44)
     .Case("hh",  VK_Sparc_HH)
     .Case("hm",  VK_Sparc_HM)
     .Case("pc22",  VK_Sparc_PC22)
     .Case("pc10",  VK_Sparc_PC10)
     .Case("got22", VK_Sparc_GOT22)
     .Case("got10", VK_Sparc_GOT10)
+    .Case("got13", VK_Sparc_GOT13)
     .Case("r_disp32",   VK_Sparc_R_DISP32)
     .Case("tgd_hi22",   VK_Sparc_TLS_GD_HI22)
     .Case("tgd_lo10",   VK_Sparc_TLS_GD_LO10)
     .Case("tgd_add",    VK_Sparc_TLS_GD_ADD)
     .Case("tgd_call",   VK_Sparc_TLS_GD_CALL)
     .Case("tldm_hi22",  VK_Sparc_TLS_LDM_HI22)
     .Case("tldm_lo10",  VK_Sparc_TLS_LDM_LO10)
     .Case("tldm_add",   VK_Sparc_TLS_LDM_ADD)
Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
   case VK_Sparc_M44:      return Sparc::fixup_sparc_m44;
   case VK_Sparc_L44:      return Sparc::fixup_sparc_l44;
   case VK_Sparc_HH:       return Sparc::fixup_sparc_hh;
   case VK_Sparc_HM:       return Sparc::fixup_sparc_hm;
   case VK_Sparc_PC22:     return Sparc::fixup_sparc_pc22;
   case VK_Sparc_PC10:     return Sparc::fixup_sparc_pc10;
   case VK_Sparc_GOT22:    return Sparc::fixup_sparc_got22;
   case VK_Sparc_GOT10:    return Sparc::fixup_sparc_got10;
+  case VK_Sparc_GOT13:    return Sparc::fixup_sparc_got13;
+  case VK_Sparc_13:       return Sparc::fixup_sparc_13;
   case VK_Sparc_WPLT30:   return Sparc::fixup_sparc_wplt30;
   case VK_Sparc_TLS_GD_HI22:   return Sparc::fixup_sparc_tls_gd_hi22;
   case VK_Sparc_TLS_GD_LO10:   return Sparc::fixup_sparc_tls_gd_lo10;
   case VK_Sparc_TLS_GD_ADD:    return Sparc::fixup_sparc_tls_gd_add;
   case VK_Sparc_TLS_GD_CALL:   return Sparc::fixup_sparc_tls_gd_call;
   case VK_Sparc_TLS_LDM_HI22:  return Sparc::fixup_sparc_tls_ldm_hi22;
   case VK_Sparc_TLS_LDM_LO10:  return Sparc::fixup_sparc_tls_ldm_lo10;
   case VK_Sparc_TLS_LDM_ADD:   return Sparc::fixup_sparc_tls_ldm_add;

lib/Target/Sparc/SparcISelLowering.cpp

 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
 // or ExternalSymbol SDNode.
 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT VT = getPointerTy(DAG.getDataLayout());
 
   // Handle PIC mode first. SPARC needs a got load for every variable!
   if (isPositionIndependent()) {
+    const Module *M = DAG.getMachineFunction().getFunction().getParent();
+    PICLevel::Level picLevel = M->getPICLevel();
+    SDValue Idx;
+
+    if (picLevel == PICLevel::SmallPIC) {
+      // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
+      Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
+                        withTargetFlags(Op, SparcMCExpr::VK_Sparc_GOT13, DAG));
+    } else {
       // This is the pic32 code model, the GOT is known to be smaller than 4GB.
-    SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
-                                SparcMCExpr::VK_Sparc_GOT10, DAG);
+      Idx = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
+    }
+
     SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
-    SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
+    SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
     // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
     // function has calls.
     MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
     MFI.setHasCalls(true);
     return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
                        MachinePointerInfo::getGOT(DAG.getMachineFunction()));
   }
 

test/CodeGen/SPARC/pic.ll

+; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck %s
+
+@value = external global i32
+
+define i32 @test() nounwind {
+; CHECK:    ld [%i0+value], %i0
+entry:
+  %0 = load i32, i32* @value
+  ret i32 %0
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 7, !"PIC Level", i32 1}

test/MC/Sparc/sparc-pic.s

 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT22 AGlobalVar 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT10 AGlobalVar 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT22 AGlobalVar 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT10 AGlobalVar 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT22 .LC0 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_GOT10 .LC0 0x0
 ! PIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_WPLT30 bar 0x0
+! PIC:        0x{{[0-9,A-F]+}} R_SPARC_GOT13 value 0x0
 ! PIC:      ]
 
 ! NOPIC:      Relocations [
 ! NOPIC-NOT:    0x{{[0-9,A-F]+}} R_SPARC_WPLT30 .text 0xC
 ! NOPIC:        0x{{[0-9,A-F]+}} R_SPARC_HI22 _GLOBAL_OFFSET_TABLE_ 0x4
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_LO10 _GLOBAL_OFFSET_TABLE_ 0x8
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_HI22 _GLOBAL_OFFSET_TABLE_ 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_LO10 _GLOBAL_OFFSET_TABLE_ 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_HI22 AGlobalVar 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_LO10 AGlobalVar 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_HI22 AGlobalVar 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_LO10 AGlobalVar 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_HI22 .rodata 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_LO10 .rodata 0x0
 ! NOPIC-NEXT:   0x{{[0-9,A-F]+}} R_SPARC_WDISP30 bar 0x0
+! NOPIC:        0x{{[0-9,A-F]+}} R_SPARC_13 value 0x0
 ! NOPIC:      ]
 
         .section        ".rodata"
         .align 8
 .LC0:
         .asciz   "string"
         .section ".text"
         .text
.Ltmp7:
 
         .type   AGlobalVar,@object      ! @AGlobalVar
         .section        .bss,#alloc,#write
         .globl  AGlobalVar
         .align  8
 AGlobalVar:
         .xword  0                       ! 0x0
         .size   AGlobalVar, 8
+
+        .section ".text"
+        .text
+        .globl  pic13
+        .align  4
+        .type   pic13,@function
+pic13:
+        save %sp, -128, %sp
+.Ltmp0:
+        call .Ltmp1
+.Ltmp2:
+        sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
+.Ltmp1:
+        or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
+        add %i0, %o7, %i0
+        ldx [%i0+value], %i0
+        ld [%i0], %i0
+        ret
+        restore
+.Lfunc_end0:
+        .size pic13, .Lfunc_end0-pic13

test/MC/Sparc/sparc-relocations.s

 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=CHECK-OBJ
 
         ! CHECK-OBJ: Format: ELF64-sparc
         ! CHECK-OBJ: Relocations [
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_WDISP30 foo
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_LO10 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HI22 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_H44 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_M44 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_L44 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym
         ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym
+        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_13 sym
         ! CHECK-ELF: ]
 
         ! CHECK: call foo     ! encoding: [0b01AAAAAA,A,A,A]
         ! CHECK:              !   fixup A - offset: 0, value: foo, kind: fixup_sparc_call30
         call foo
 
         ! CHECK: or %g1, %lo(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A]
         ! CHECK-NEXT:                  !   fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=CHECK-OBJ
 
         ! CHECK: sethi %hh(sym), %l0  ! encoding: [0x21,0b00AAAAAA,A,A]
         ! CHECK-NEXT:                 !   fixup A - offset: 0, value: %hh(sym), kind: fixup_sparc_hh
         sethi %hh(sym), %l0
 
         ! CHECK: or %g1, %hm(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A]
         ! CHECK-NEXT:                  !   fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm
         or %g1, %hm(sym), %g3
+
+        ! CHECK: or %g1, sym, %g3 ! encoding: [0x86,0x10,0b011AAAAA,A]
+        ! CHECK-NEXT:                  !   fixup A - offset: 0, value: sym, kind: fixup_sparc_13
+        or %g1, sym, %g3