[Hexagon] Generate post-increment for floating point types

[bcahoon]

Summary

The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64.

llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

case MVT::i8:
     break;
   case MVT::i16:
     if (IsZeroExt)
       Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
     else
       Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
     break;
   case MVT::i32:
+  case MVT::f32:
   case MVT::v2i16:
   case MVT::v4i8:
     Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
     break;
   case MVT::i64:
+  case MVT::f64:
   case MVT::v2i32:
   case MVT::v4i16:
   case MVT::v8i8:
     Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
     break;
   case MVT::v64i8:
   case MVT::v32i16:
   case MVT::v16i32:
void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
   switch (StoredVT.getSimpleVT().SimpleTy) {
   case MVT::i8:
     Opcode = IsValidInc ? Hexagon::S2_storerb_pi : Hexagon::S2_storerb_io;
     break;
   case MVT::i16:
     Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
     break;
   case MVT::i32:
+  case MVT::f32:
   case MVT::v2i16:
   case MVT::v4i8:
     Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
     break;
   case MVT::i64:
+  case MVT::f64:
   case MVT::v2i32:
   case MVT::v4i16:
   case MVT::v8i8:
     Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
     break;
   case MVT::v64i8:
   case MVT::v32i16:
   case MVT::v16i32:

llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
       SelectionDAG &DAG) const {
   LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
   if (!LSN)
     return false;
   EVT VT = LSN->getMemoryVT();
   if (!VT.isSimple())
     return false;
   bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
-                     VT == MVT::i64 || VT == MVT::v2i16 || VT == MVT::v2i32 ||
-                     VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v8i8 ||
+                     VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
+                     VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
+                     VT == MVT::v4i16 || VT == MVT::v8i8 ||
                      Subtarget.isHVXVectorType(VT.getSimpleVT());
   if (!IsLegalType)
     return false;
 
   if (Op->getOpcode() != ISD::ADD)
     return false;
   Base = Op->getOperand(0);
   Offset = Op->getOperand(1);
for (ISD::CondCode FPExpCCV4 :
           ISD::SETUO,  ISD::SETO}) {
       setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
       setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
     }
   }
 
   // Handling of indexed loads/stores: default is "expand".
   //
-  for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::v2i16,
-                 MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
+  for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
+                 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
     setIndexedLoadAction(ISD::POST_INC, VT, Legal);
     setIndexedStoreAction(ISD::POST_INC, VT, Legal);
   }
 
   if (Subtarget.useHVXOps())
     initializeHVXLowering();
 
   computeRegisterProperties(&HRI);

llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
   int Count = Offset / Size;
 
   switch (VT.getSimpleVT().SimpleTy) {
     // For scalars the auto-inc is s4
     case MVT::i8:
     case MVT::i16:
     case MVT::i32:
     case MVT::i64:
+    case MVT::f32:
+    case MVT::f64:
     case MVT::v2i16:
     case MVT::v2i32:
     case MVT::v4i8:
     case MVT::v4i16:
     case MVT::v8i8:
       return isInt<4>(Count);
     // For HVX vectors the auto-inc is s3
     case MVT::v64i8:

llvm/trunk/test/CodeGen/Hexagon/postinc-float.ll

+; RUN: llc -mtriple=hexagon-unknown-elf < %s | FileCheck %s
+
+; CHECK-LABEL: ldf
+; CHECK: memw(r{{[0-9]+}}++#4)
+; CHECK: memw(r{{[0-9]+}}++#4)
+define float @ldf(float* nocapture readonly %x, float* nocapture readonly %y) local_unnamed_addr #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi float* [ %x, %entry ], [ %arrayidx.inc, %for.body ]
+  %arrayidx1.phi = phi float* [ %y, %entry ], [ %arrayidx1.inc, %for.body ]
+  %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %acc.08 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+  %0 = load float, float* %arrayidx.phi, align 4
+  %1 = load float, float* %arrayidx1.phi, align 4
+  %mul = fmul contract float %0, %1
+  %add = fadd contract float %acc.08, %mul
+  %inc = add nuw nsw i32 %i.09, 1
+  %exitcond = icmp eq i32 %inc, 1024
+  %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
+  %arrayidx1.inc = getelementptr float, float* %arrayidx1.phi, i32 1
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret float %add
+}
+
+; CHECK-LABEL: ldd
+; CHECK: memd(r{{[0-9]+}}++#8)
+; CHECK: memd(r{{[0-9]+}}++#8)
+define double @ldd(double* nocapture readonly %x, double* nocapture readonly %y) local_unnamed_addr #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi double* [ %x, %entry ], [ %arrayidx.inc, %for.body ]
+  %arrayidx1.phi = phi double* [ %y, %entry ], [ %arrayidx1.inc, %for.body ]
+  %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %acc.08 = phi double [ 0.000000e+00, %entry ], [ %add, %for.body ]
+  %0 = load double, double* %arrayidx.phi, align 8
+  %1 = load double, double* %arrayidx1.phi, align 8
+  %mul = fmul contract double %0, %1
+  %add = fadd contract double %acc.08, %mul
+  %inc = add nuw nsw i32 %i.09, 1
+  %exitcond = icmp eq i32 %inc, 1024
+  %arrayidx.inc = getelementptr double, double* %arrayidx.phi, i32 1
+  %arrayidx1.inc = getelementptr double, double* %arrayidx1.phi, i32 1
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret double %add
+}
+
+; CHECK-LABEL: stf
+; CHECK: memw(r{{[0-9]+}}++#4)
+define double* @stf(float* returned %p) local_unnamed_addr #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi float* [ %arrayidx.inc, %for.body ], [ %p, %entry ]
+  %call = tail call float @foof() #2
+  store float %call, float* %arrayidx.phi, align 8
+  %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
+  br label %for.body
+}
+
+declare float @foof() local_unnamed_addr #1
+
+; CHECK-LABEL: std
+; CHECK: memd(r{{[0-9]+}}++#8)
+define double* @std(double* returned %p) local_unnamed_addr #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %arrayidx.phi = phi double* [ %arrayidx.inc, %for.body ], [ %p, %entry ]
+  %call = tail call double @food() #2
+  store double %call, double* %arrayidx.phi, align 8
+  %arrayidx.inc = getelementptr double, double* %arrayidx.phi, i32 1
+  br label %for.body
+}
+
+declare double @food() local_unnamed_addr #1
+

llvm/trunk/test/CodeGen/Hexagon/swp-memrefs-epilog.ll

 ; RUN: llc -march=hexagon -O2 -fp-contract=fast < %s | FileCheck %s
 
 ; Test that the memoperands for instructions in the epilog are updated
 ; correctly. Previously, the pipeliner updated the offset for the memoperands
 ; in the epilog. But, the value of the offset is incorrect when control flow
 ; branches around the kernel.
 
 ; In this test, we check that a load and store to the same location are not
 ; swapped due to a bad offset in the memoperands. The store and load are both
 ; to r29+32. If the memoperands are updated incorrectly, these are swapped.
 
 ; CHECK: [[REG0:r([0-9]+)]] = add(r29,#24)
-; CHECK: [[REG1:r([0-9]+)]] = add([[REG0]],#4)
-; CHECK: memw([[REG1]]+#{{[0-9]}}) = r{{[0-9]+}}
+; CHECK: memw([[REG0]]++#4) = r{{[0-9]+}}
 ; CHECK: r{{[0-9]+}} = memw(r29+#{{[0-9]+}})
 
 %s.0 = type { %s.1 }
 %s.1 = type { %s.2 }
 %s.2 = type { %s.3 }
 %s.3 = type { [9 x float] }
 %s.4 = type { %s.5 }
 %s.5 = type { %s.6 }