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Differential D46949

[mips] Correct the predicates of the cache and pref instructions
ClosedPublic

Authored by sdardis on May 16 2018, 8:22 AM.

Details

Reviewers
atanasyan
abeserminji
smaksimovic
Commits
rG437153bb8022: [mips] Correct the predicates of the cache and pref instructions
rL332970: [mips] Correct the predicates of the cache and pref instructions

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.May 16 2018, 8:22 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 16 2018, 8:22 AM
atanasyan accepted this revision.May 17 2018, 8:47 AM

LGTM

This revision is now accepted and ready to land.May 17 2018, 8:47 AM
Closed by commit rL332970: [mips] Correct the predicates of the cache and pref instructions (authored by sdardis). · Explain WhyMay 22 2018, 3:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
14 lines
6 lines
10 lines
test/
MC/
Mips/
micromips/
2 lines
micromips32r6/
2 lines
mips32r6/
2 lines

Diff 147982

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 1,046 Lines • ▼ Show 20 Lines def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>, def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>, def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
ISA_MICROMIPS, ASE_EVA; ISA_MICROMIPS, ASE_EVA;
def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>, def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
ISA_MICROMIPS, ASE_EVA; ISA_MICROMIPS, ASE_EVA;
}
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
let DecoderMethod = "DecodeCacheOpMM" in { let DecoderMethod = "DecodeCacheOpMM" in {
def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>, def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
CACHE_PREF_FM_MM<0x08, 0x6>; CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>, def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
CACHE_PREF_FM_MM<0x18, 0x2>; CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
} }
}
let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodePrefeOpMM" in { let DecoderMethod = "DecodePrefeOpMM" in {
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>, def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA; CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>, def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA; CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
} }
def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>, def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
ISA_MICROMIPS; ISA_MICROMIPS;
▲ Show 20 Lines • Show All 302 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 882 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
}
def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT; def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT; def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
} }
def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>; defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>; defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
Show All 36 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
} }
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
HARDFLOAT; HARDFLOAT;
▲ Show 20 Lines • Show All 178 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 2,448 Lines • ▼ Show 20 Lines
class CacheOp<string instr_asm, Operand MemOpnd, class CacheOp<string instr_asm, Operand MemOpnd,
InstrItinClass itin = NoItinerary> : InstrItinClass itin = NoItinerary> :
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
!strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther, !strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther,
instr_asm> { instr_asm> {
let DecoderMethod = "DecodeCacheOp"; let DecoderMethod = "DecodeCacheOp";
} }
let AdditionalPredicates = [NotInMicroMips] in {
def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>, def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,
INSN_MIPS3_32_NOT_32R6_64R6; INSN_MIPS3_32_NOT_32R6_64R6;
def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>, def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
INSN_MIPS3_32_NOT_32R6_64R6; INSN_MIPS3_32_NOT_32R6_64R6;
}
// FIXME: We are missing the prefx instruction. // FIXME: We are missing the prefx instruction.
def ROL : MipsAsmPseudoInst<(outs), def ROL : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
"rol\t$rs, $rt, $rd">; "rol\t$rs, $rt, $rd">;
def ROLImm : MipsAsmPseudoInst<(outs), def ROLImm : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
"rol\t$rs, $rt, $imm">; "rol\t$rs, $rt, $imm">;
def : MipsInstAlias<"rol $rd, $rs", def : MipsInstAlias<"rol $rd, $rs",
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
tne $8, $9 # CHECK: tne $8, $9 # encoding: [0x01,0x28,0x0c,0x3c] tne $8, $9 # CHECK: tne $8, $9 # encoding: [0x01,0x28,0x0c,0x3c]
teqi $9, 17767 # CHECK: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67] teqi $9, 17767 # CHECK: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67]
tgei $9, 17767 # CHECK: tgei $9, 17767 # encoding: [0x41,0x29,0x45,0x67] tgei $9, 17767 # CHECK: tgei $9, 17767 # encoding: [0x41,0x29,0x45,0x67]
tgeiu $9, 17767 # CHECK: tgeiu $9, 17767 # encoding: [0x41,0x69,0x45,0x67] tgeiu $9, 17767 # CHECK: tgeiu $9, 17767 # encoding: [0x41,0x69,0x45,0x67]
tlti $9, 17767 # CHECK: tlti $9, 17767 # encoding: [0x41,0x09,0x45,0x67] tlti $9, 17767 # CHECK: tlti $9, 17767 # encoding: [0x41,0x09,0x45,0x67]
tltiu $9, 17767 # CHECK: tltiu $9, 17767 # encoding: [0x41,0x49,0x45,0x67] tltiu $9, 17767 # CHECK: tltiu $9, 17767 # encoding: [0x41,0x49,0x45,0x67]
tnei $9, 17767 # CHECK: tnei $9, 17767 # encoding: [0x41,0x89,0x45,0x67] tnei $9, 17767 # CHECK: tnei $9, 17767 # encoding: [0x41,0x89,0x45,0x67]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} CACHE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} PREF_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00] ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00]
pause # CHECK: pause # encoding: [0x00,0x00,0x28,0x00] pause # CHECK: pause # encoding: [0x00,0x00,0x28,0x00]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
lwxs $2, $3($4) # CHECK: lwxs $2, $3($4) # encoding: [0x00,0x64,0x11,0x18] lwxs $2, $3($4) # CHECK: lwxs $2, $3($4) # encoding: [0x00,0x64,0x11,0x18]
bgezals $6, 1332 # CHECK: bgezals $6, 1332 # encoding: [0x42,0x66,0x02,0x9a] bgezals $6, 1332 # CHECK: bgezals $6, 1332 # encoding: [0x42,0x66,0x02,0x9a]
bltzals $6, 1332 # CHECK: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a] bltzals $6, 1332 # CHECK: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a]
▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show All 40 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a] beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a]
bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a] bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a]
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
break # CHECK: break # encoding: [0x00,0x00,0x00,0x07] break # CHECK: break # encoding: [0x00,0x00,0x00,0x07]
break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07] break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07]
break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} CACHE_MMR6
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c] clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18] div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98] divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00] ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00]
ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2] ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
# CHECK-NEXT: # <MCInst #{{.*}} PREF_MMR6
sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84] sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84]
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c] seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c] seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c]
seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c] seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
seh $3 # CHECK: seh $3, $3 # encoding: [0x00,0x63,0x3b,0x3c] seh $3 # CHECK: seh $3, $3 # encoding: [0x00,0x63,0x3b,0x3c]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
sh16 $4, 8($17) # CHECK: sh16 $4, 8($17) # encoding: [0xaa,0x14] sh16 $4, 8($17) # CHECK: sh16 $4, 8($17) # encoding: [0xaa,0x14]
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llvm/trunk/test/MC/Mips/mips32r6/valid.s

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bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01]
bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01]
bnvc $2, $4, 4 # CHECK: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01] bnvc $2, $4, 4 # CHECK: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01]
# bovc requires that rs >= rt but we accept both and fix this. See also beqc. # bovc requires that rs >= rt but we accept both and fix this. See also beqc.
bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01]
bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01]
bovc $2, $4, 4 # CHECK: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01] bovc $2, $4, 4 # CHECK: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25]
# CHECK-NEXT: # <MCInst #{{.*}} CACHE_R6
ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce] ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
# CHECK: # <MCInst #{{.*}} CEIL_W_D64 # CHECK: # <MCInst #{{.*}} CEIL_W_D64
ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e] ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
# CHECK: # <MCInst #{{.*}} CEIL_W_S # CHECK: # <MCInst #{{.*}} CEIL_W_S
cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81]
cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81]
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negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27] not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27] not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# CHECK-NEXT: # <MCInst #{{.*}} PREF_R6
# FIXME: Use the code generator in order to print the .set directives # FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer. # instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2 # CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11 # CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c] round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c]
# CHECK: # <MCInst #{{.*}} ROUND_W_D64 # CHECK: # <MCInst #{{.*}} ROUND_W_D64
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