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Differential D46692

[mips] Fix predicates of mfc1, mtc1 instructions
ClosedPublic

Authored by sdardis on May 10 2018, 5:37 AM.

Details

Reviewers
atanasyan
abeserminji
smaksimovic
Commits
rGb79ecec20d56: [mips] Fix predicates of mfc1, mtc1 instructions
rL332339: [mips] Fix predicates of mfc1, mtc1 instructions

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.May 10 2018, 5:37 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 10 2018, 5:37 AM
atanasyan accepted this revision.May 10 2018, 10:56 PM

LGTM

This revision is now accepted and ready to land.May 10 2018, 10:56 PM
Closed by commit rL332339: [mips] Fix predicates of mfc1, mtc1 instructions (authored by sdardis). · Explain WhyMay 15 2018, 4:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
17 lines
33 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
4 lines
4 lines
4 lines
4 lines
Mips/
8 lines

Diff 146781

llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
let isCodeGenOnly = 1 in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS; ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS; ISA_MICROMIPS;
}
let DecoderNamespace = "MicroMips" in {
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>, def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>, def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>, def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>, def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

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// stores, and moves between floating-point and integer registers. // stores, and moves between floating-point and integer registers.
// When defining instructions, we reference all 32-bit registers, // When defining instructions, we reference all 32-bit registers,
// regardless of register aliasing. // regardless of register aliasing.
/// Move Control Registers From/To CPU Registers /// Move Control Registers From/To CPU Registers
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
}
def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
bitconvert>, MFC1_FM<0>; bitconvert>, MFC1_FM<0>;
def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
FGR_64 { FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
bitconvert>, MFC1_FM<4>; bitconvert>, MFC1_FM<4>;
def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
FGR_64 { FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
let AdditionalPredicates = [NotInMicroMips] in {
def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_32; MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
}
let AdditionalPredicates = [NotInMicroMips] in {
def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_32; MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
} }
}
let AdditionalPredicates = [NotInMicroMips] in {
def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
bitconvert>, MFC1_FM<5>, ISA_MIPS3; bitconvert>, MFC1_FM<5>, ISA_MIPS3;
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
bitconvert>, MFC1_FM<1>, ISA_MIPS3; bitconvert>, MFC1_FM<1>, ISA_MIPS3;
def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABSS_FM<0x6, 16>; ABSS_FM<0x6, 16>;
def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
ABSS_FM<0x6, 17>, FGR_32; ABSS_FM<0x6, 17>, FGR_32;
▲ Show 20 Lines • Show All 410 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

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0xc8 0x54 0x3b 0x09 # CHECK: cvt.w.s $f6, $f8 0xc8 0x54 0x3b 0x09 # CHECK: cvt.w.s $f6, $f8
0xc8 0x54 0x3b 0x49 # CHECK: cvt.w.d $f6, $f8 0xc8 0x54 0x3b 0x49 # CHECK: cvt.w.d $f6, $f8
0xc8 0x54 0x3b 0x0b # CHECK: floor.w.s $f6, $f8 0xc8 0x54 0x3b 0x0b # CHECK: floor.w.s $f6, $f8
0xc8 0x54 0x3b 0x4b # CHECK: floor.w.d $f6, $f8 0xc8 0x54 0x3b 0x4b # CHECK: floor.w.d $f6, $f8
0xc8 0x54 0x3b 0x3b # CHECK: round.w.s $f6, $f8 0xc8 0x54 0x3b 0x3b # CHECK: round.w.s $f6, $f8
0xc8 0x54 0x3b 0x7b # CHECK: round.w.d $f6, $f8 0xc8 0x54 0x3b 0x7b # CHECK: round.w.d $f6, $f8
0xc8 0x54 0x3b 0x2b # CHECK: trunc.w.s $f6, $f8 0xc8 0x54 0x3b 0x2b # CHECK: trunc.w.s $f6, $f8
0xc8 0x54 0x3b 0x6b # CHECK: trunc.w.d $f6, $f8 0xc8 0x54 0x3b 0x6b # CHECK: trunc.w.d $f6, $f8
0x86 0x54 0x3b 0x28 # CHECK: mtc1 $4, $f6
0x86 0x54 0x3b 0x20 # CHECK: mfc1 $4, $f6
0x86 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f6
0x86 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f6

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt

Show All 15 Lines
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2 0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2 0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5) 0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5)
0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5) 0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5)
0x86 0x54 0x3b 0x28 # CHECK: mtc1 $4, $f6
0x86 0x54 0x3b 0x20 # CHECK: mfc1 $4, $f6
0x86 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f6
0x86 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f6

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt

Show All 15 Lines
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2 0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2 0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5) 0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5)
0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5) 0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5)
0x54 0x86 0x28 0x3b # CHECK: mtc1 $4, $f6
0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

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0x54 0xc8 0x09 0x3b # CHECK: cvt.w.s $f6, $f8 0x54 0xc8 0x09 0x3b # CHECK: cvt.w.s $f6, $f8
0x54 0xc8 0x49 0x3b # CHECK: cvt.w.d $f6, $f8 0x54 0xc8 0x49 0x3b # CHECK: cvt.w.d $f6, $f8
0x54 0xc8 0x0b 0x3b # CHECK: floor.w.s $f6, $f8 0x54 0xc8 0x0b 0x3b # CHECK: floor.w.s $f6, $f8
0x54 0xc8 0x4b 0x3b # CHECK: floor.w.d $f6, $f8 0x54 0xc8 0x4b 0x3b # CHECK: floor.w.d $f6, $f8
0x54 0xc8 0x3b 0x3b # CHECK: round.w.s $f6, $f8 0x54 0xc8 0x3b 0x3b # CHECK: round.w.s $f6, $f8
0x54 0xc8 0x7b 0x3b # CHECK: round.w.d $f6, $f8 0x54 0xc8 0x7b 0x3b # CHECK: round.w.d $f6, $f8
0x54 0xc8 0x2b 0x3b # CHECK: trunc.w.s $f6, $f8 0x54 0xc8 0x2b 0x3b # CHECK: trunc.w.s $f6, $f8
0x54 0xc8 0x6b 0x3b # CHECK: trunc.w.d $f6, $f8 0x54 0xc8 0x6b 0x3b # CHECK: trunc.w.d $f6, $f8
0x54 0x86 0x28 0x3b # CHECK: mtc1 $4, $f6
0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6

llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s

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# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b] # CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b] # CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10] # CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18] # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20] # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MFC1_MM
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28] # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MTC1_MM
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30] # CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38] # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20] # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21] # CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20] # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21] # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
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# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b] # CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b] # CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b] # CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b] # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b] # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MFC1_MM
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b] # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MTC1_MM
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b] # CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b] # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78] # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78] # CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38] # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38] # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
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