[X86] ptwrite intrinsic

[craig.topper]

lib/Target/X86/X86.td

641 ↗

(On Diff #145509)

does Tremont have PTWrite?

[GBuella]

lib/Target/X86/X86.td

641 ↗

(On Diff #145509)

Oh, it does indeed.

[GBuella]

Rearranged proc features in X86.td

[RKSimon]

lib/Target/X86/X86.td

623 ↗

(On Diff #145509)

Just put FeaturePTWRITE here?

test/CodeGen/X86/ptwrite-intrinsic-x86.ll

2 ↗

(On Diff #145509)

Possibly test all the i32 versions here on both x86/x64 and just test the i64 versions in the x86_64.ll file.

12 ↗

(On Diff #145509)

Can you add tests for the reg-reg version as well?

[craig.topper]

lib/Target/X86/X86.td

623 ↗

(On Diff #145509)

It's not on GLM. Just GLP and Tremont.

[craig.topper]

test/CodeGen/X86/ptwrite-intrinsic-x86.ll

12 ↗

(On Diff #145509)

I see this is fixed now, but not the comment above?

[RKSimon]

LGTM with one minor

lib/Target/X86/X86InstrSystem.td

691 ↗

(On Diff #145923)

Possibly add an extra description (as discussed on D46540) here:

// PTWRITE Instruction - Write Processor Trace (PTW) Packet

llvm/trunk/include/llvm/IR/IntrinsicsX86.td

 let TargetPrefix = "x86" in {
   def int_x86_directstore32 : GCCBuiltin<"__builtin_ia32_directstore_u32">,
       Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
   def int_x86_directstore64 : GCCBuiltin<"__builtin_ia32_directstore_u64">,
       Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
   def int_x86_movdir64b : GCCBuiltin<"__builtin_ia32_movdir64b">,
       Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], []>;
 }
+
+//===----------------------------------------------------------------------===//
+// PTWrite - Write data to processor trace pocket
+
+let TargetPrefix = "x86" in {
+  def int_x86_ptwrite32 : GCCBuiltin<"__builtin_ia32_ptwrite32">,
+              Intrinsic<[], [llvm_i32_ty], []>;
+  def int_x86_ptwrite64 : GCCBuiltin<"__builtin_ia32_ptwrite64">,
+              Intrinsic<[], [llvm_i64_ty], []>;
+}

llvm/trunk/lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
   Features["xsavec"]   = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
   Features["xsaves"]   = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
 
+  bool HasLeaf14 = MaxLevel >= 0x14 &&
+                  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
+
+  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
+
   return true;
 }
 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
   if (!P)
     return false;
 

llvm/trunk/lib/Target/X86/X86.td

 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
                                        "Support LAHF and SAHF instructions">;
 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
                                       "Enable MONITORX/MWAITX timer functionality">;
 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
                                       "Enable Cache Line Zero">;
 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
                                       "Enable Cache Demote">;
+def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
+                                      "Support ptwrite instruction">;
 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
                                       "Support MPX instructions">;
 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
                                      "Use LEA for adjusting the stack pointer">;
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",

 
 class GoldmontProc<string Name> : ProcModel<Name, SLMModel,
       GLMFeatures.Value, [
   ProcIntelGLM,
   FeaturePOPCNTFalseDeps
 ]>;
 def : GoldmontProc<"goldmont">;
 
-class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
-      GLMFeatures.Value, [
-  ProcIntelGLP,
+def GLPFeatures : ProcessorFeatures<GLMFeatures.Value, [
+  FeaturePTWRITE,
   FeatureRDPID,
   FeatureSGX
 ]>;
+
+class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
+      GLPFeatures.Value, [
+  ProcIntelGLP
+]>;
 def : GoldmontPlusProc<"goldmont-plus">;
 
 class TremontProc<string Name> : ProcModel<Name, SLMModel,
-      GLMFeatures.Value, [
+      GLPFeatures.Value, [
   ProcIntelTRM,
   FeatureCLDEMOTE,
   FeatureGFNI,
   FeatureMOVDIRI,
   FeatureMOVDIR64B,
-  FeatureRDPID,
-  FeatureSGX,
   FeatureWAITPKG
 ]>;
 def : TremontProc<"tremont">;
 
 // "Arrandale" along with corei3 and corei5
 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
   FeatureX87,
   FeatureMMX,

llvm/trunk/lib/Target/X86/X86InstrInfo.td

 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
 def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
+def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasIBT       : Predicate<"Subtarget->hasIBT()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;

llvm/trunk/lib/Target/X86/X86InstrSystem.td

let Predicates = [In64BitMode, HasRDPID] in {
   // Due to silly instruction definition, we have to compensate for the
   // instruction outputing a 64-bit register.
   def : Pat<(int_x86_rdpid),
             (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
 }
 
 
 //===----------------------------------------------------------------------===//
-// PTWRITE Instruction
+// PTWRITE Instruction - Write Data to a Processor Trace Packet
 let SchedRW = [WriteSystem] in {
-
 def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
-                "ptwrite{l}\t$dst", []>, XS;
+                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
+                Requires<[HasPTWRITE]>;
 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
-                    "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
+                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
+                    Requires<[In64BitMode, HasPTWRITE]>;
 
 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
-                 "ptwrite{l}\t$dst", []>, XS;
+                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
+                    Requires<[HasPTWRITE]>;
 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
-                    "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
+                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
+                    Requires<[In64BitMode, HasPTWRITE]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
 // Platform Configuration instruction
 
 // From ISA docs:
 //  "This instruction is used to execute functions for configuring platform
 //   features.
 //   EAX: Leaf function to be invoked.
 //   RBX/RCX/RDX: Leaf-specific purpose."
 //  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
 //   AF, OF, and SF are cleared. In case of failure, the failure reason is
 //   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
 // Thus all these mentioned registers are considered clobbered.
 
 let SchedRW = [WriteSystem] in {
 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
     def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
                   Requires<[HasPCONFIG]>;
-} // SchedRW
+} // SchedRW
 

llvm/trunk/lib/Target/X86/X86Subtarget.h

protected:
   bool HasCLDEMOTE;
 
   /// Processor has MOVDIRI instruction (direct store integer).
   bool HasMOVDIRI;
 
   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
   bool HasMOVDIR64B;
 
+  /// Processor has ptwrite instruction.
+  bool HasPTWRITE;
+
   /// Processor has Prefetch with intent to Write instruction
   bool HasPREFETCHWT1;
 
   /// True if SHLD instructions are slow.
   bool IsSHLDSlow;
 
   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
   //  PMULUDQ.
public:
   }
   bool hasRDSEED() const { return HasRDSEED; }
   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
   bool hasMWAITX() const { return HasMWAITX; }
   bool hasCLZERO() const { return HasCLZERO; }
   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
   bool hasMOVDIRI() const { return HasMOVDIRI; }
   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
+  bool hasPTWRITE() const { return HasPTWRITE; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isPMULLDSlow() const { return IsPMULLDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
   int getGatherOverhead() const { return GatherOverhead; }
   int getScatterOverhead() const { return ScatterOverhead; }
   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
   bool hasCmpxchg16b() const { return HasCmpxchg16b; }

llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+ptwrite | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ptwrite | FileCheck %s --check-prefix=X86_64
+
+define void @test_ptwrite(i32 %value) {
+; X86-LABEL: test_ptwrite:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    ptwritel {{[0-9]+}}(%esp)
+; X86-NEXT:    retl
+;
+; X86_64-LABEL: test_ptwrite:
+; X86_64:       # %bb.0: # %entry
+; X86_64-NEXT:    ptwritel %edi
+; X86_64-NEXT:    retq
+entry:
+  call void @llvm.x86.ptwrite32(i32 %value)
+  ret void
+}
+
+define void @test_ptwrite2(i32 %x) {
+; X86-LABEL: test_ptwrite2:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    incl %eax
+; X86-NEXT:    ptwritel %eax
+; X86-NEXT:    retl
+;
+; X86_64-LABEL: test_ptwrite2:
+; X86_64:       # %bb.0: # %entry
+; X86_64-NEXT:    incl %edi
+; X86_64-NEXT:    ptwritel %edi
+; X86_64-NEXT:    retq
+entry:
+  %value = add i32 %x, 1
+  call void @llvm.x86.ptwrite32(i32 %value)
+  ret void
+}
+
+define void @test_ptwrite32p(i32* %pointer) {
+; X86-LABEL: test_ptwrite32p:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    ptwritel (%eax)
+; X86-NEXT:    retl
+;
+; X86_64-LABEL: test_ptwrite32p:
+; X86_64:       # %bb.0: # %entry
+; X86_64-NEXT:    ptwritel (%rdi)
+; X86_64-NEXT:    retq
+entry:
+  %value = load i32, i32* %pointer, align 4
+  call void @llvm.x86.ptwrite32(i32 %value)
+  ret void
+}
+
+declare void @llvm.x86.ptwrite32(i32)

llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ptwrite | FileCheck %s
+
+define void @test_ptwrite64(i64 %value) {
+; CHECK-LABEL: test_ptwrite64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ptwriteq %rdi
+; CHECK-NEXT:    retq
+entry:
+  call void @llvm.x86.ptwrite64(i64 %value)
+  ret void
+}
+
+define void @test_ptwrite64p(i64* %pointer) {
+; CHECK-LABEL: test_ptwrite64p:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ptwriteq (%rdi)
+; CHECK-NEXT:    retq
+entry:
+  %value = load i64, i64* %pointer, align 8
+  call void @llvm.x86.ptwrite64(i64 %value)
+  ret void
+}
+
+declare void @llvm.x86.ptwrite64(i64)